Datasheet AOZ5273QI (Alpha & Omega) - 3

AOZ5273QI Pin Description Pin Number Pin Name Pin Function
1 VOS Output voltage sense. 2 AGND Signal Ground. 5 V Bias for Internal Logic Blocks. Ensure to position a 1 µF MLCC directly between VCC and 3 VCC AGND (Pin 2). 5 V Power Rail for High-Side and Low-Side MOSFET Drivers. Ensure to position a 1µF MLCC 4 PVCC directly between PVCC and PGND (Pin 5). Power Ground for High-Side and Low-Side MOSFET Gate Drivers. Ensure to connect 1µF 5, 40 PGND MLCC directly between PGND and PVCC (Pin 4). 6, 41 GL Low-Side MOSFET Gate connection. This is for test purposes only. 7, 8, 9, 20, 21, PGND Power Ground pin for power stage (Source connection of Low-Side MOSFET). 22, 23, 24 10, 11, 12, 13, Switching node connected to the Source of High-Side MOSFET and the Drain of Low-Side 14, 15, 16, 17, VSWH MOSFET. 18, 19 25, 26, 27, 28, VIN Power stage High Voltage Input (Drain connection of High-Side MOSFET). 29, 30 31, 32 PHASE This pin is dedicated for bootstrap capacitor AC return path connection from BOOT (Pin 33). High-Side MOSFET Gate Driver supply rail. Connect a 100nF ceramic capacitor between 33 BOOT BOOT and the PHASE (Pin 31 and 32). PWM input signal from Controller IC. This input is compatible with 3.3V and 5V Tri-State logic 34 PWM levels. Output enable pin. When this pin is pulled to a logic low level, the IC disables most blocks. 35 EN EN=HIGH enables all blocks inside IC and requires 4µs power up time. Temperature Monitor and Fault Flag Pin. TMON/FLT will be pulled HI (~ 3.3 V) or LOW (0V) to indicate a fault condition (see Table 5). For multi-phase application, the TMON/FLT pin can be connected together as a common bus. The highest voltage representing the highest temperature among all phases will be sent to the PWM controller. No more than 470pF total 36 TMON/FLT capacitance can be directly connected across TMON/FLT and AGND (Pin 2). A higher capacitance load is allowed with a series resistor (~ 1kΩ) for up to 1nF. At 0°C and in normal operation, the output voltage is 0.6V with a temperature coefficient value of 8mV/°C. There is an internal pull up source to 3.3V when a fault condition occurs. Setting control for OCP limit threshold and Zero Cross Detect function (ZCD). OCP limit threshold is detected and latched 120µs after device enabled. Refer to Table 3 for the resistor 37 OCSET/ZCD value for each current limit threshold level. After 120µs, the OCP limit is set and this pin becomes ZCD control only. ZCD is active when this pin is floating or pulled HI. Current Monitor output signal referenced to REFIN (Pin 39). Connect the IMON output to the appropriate Current Sense input of the controller. No more than 47pF capacitance can be 38 IMON directly connected across IMON and REFIN pins. With a 100Ω series resistor, up to 470pF may be used. Input for external reference voltage for IMON (Pin 38). This voltage should be between 0.7 V and 2.0V. Nominal value is 1.2V. Place a low ESR ceramic capacitor (~ 0.1µF) from this pin to 39 REFIN AGND (Pin 2). Connect REFIN to the appropriate Current Sense Reference output from the controller. Rev.2.0 April 2021
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