Datasheet STB9NK90Z, STF9NK90Z, STP9NK90Z, STW9NK90Z (STMicroelectronics) - 4
| 制造商 | STMicroelectronics |
| 描述 | N-channel 900 V, 1.1 Ω, 8 A, TO-220, TO-220FP, D2PAK, TO-247 Zener-protected SuperMESH Power MOSFET |
| 页数 / 页 | 17 / 4 — Electrical characteristics. STB9NK90Z, STF9NK90Z, STP9NK90Z, STW9NK90Z. 2 … |
| 文件格式/大小 | PDF / 1.0 Mb |
| 文件语言 | 英语 |
Electrical characteristics. STB9NK90Z, STF9NK90Z, STP9NK90Z, STW9NK90Z. 2 Electrical. characteristics. Table 5. On/off states
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Electrical characteristics STB9NK90Z, STF9NK90Z, STP9NK90Z, STW9NK90Z 2 Electrical characteristics
(TCASE = 25 °C unless otherwise specified)
Table 5. On/off states Symbol Parameter Test conditions Min. Typ. Max. Unit
Drain-source breakdown V(BR)DSS I voltage D = 1 mA, VGS= 0 900 V Zero gate voltage drain V 1 µA I DS = max rating, DSS current (VGS = 0) VDS = max rating @125 °C 50 µA Gate body leakage current IGSS V (V GS = ± 20 V, VDS = 0 ±10 µA DS = 0) VGS(th) Gate threshold voltage VDS = VGS, ID = 100 µA 3 3.75 4.5 V Static drain-source on RDS(on) V resistance GS = 10 V, ID = 3.6 A 1.1 1.3 Ω
Table 6. Dynamic Symbol Parameter Test conditions Min. Typ. Max. Unit
Input capacitance Ciss 2115 pF Output capacitance V C DS = 25 V, f = 1 MHz, oss - 190 - pF Reverse transfer VGS = 0 Crss 40 pF capacitance Equivalent output C (1) oss eq V capacitance GS = 0, VDS = 0 to 720 V - 115 - pF Qg Total gate charge VDD = 720 V, ID = 8 A 72 nC Qgs Gate-source charge VGS =10 V - 14 - nC Q Figure 20 gd Gate-drain charge 38 nC 1. Coss eq. is defined as a constant equivalent capacitance giving the same charging time as Coss when VDS increases from 0 to 80% VDSS 4/17 Doc ID 9479 Rev 7 Document Outline Figure 1. Internal schematic diagram Table 1. Device summary 1 Electrical ratings Table 2. Absolute maximum ratings Table 3. Thermal data Table 4. Avalanche characteristics 2 Electrical characteristics Table 5. On/off states Table 6. Dynamic Table 7. Switching times Table 8. Source drain diode Table 9. Gate-source Zener diode 2.1 Electrical characteristics (curves) Figure 2. Safe operating area for TO-220, D·PAK Figure 3. Thermal impedance for TO-220, D·PAK Figure 4. Safe operating area for TO-220FP Figure 5. Thermal impedance for TO-220FP Figure 6. Safe operating area for TO-247 Figure 7. Thermal impedance for TO-247 Figure 8. Output characteristics Figure 9. Transfer characteristics Figure 10. Transconductance Figure 11. Static drain-source on resistance Figure 12. Gate charge vs gate-source voltage Figure 13. Capacitance variations Figure 14. Normalized gate threshold voltage vs temperature Figure 15. Normalized on resistance vs temperature Figure 16. Source-drain diode forward characteristics Figure 17. Normalized BVDSS vs temperature Figure 18. Maximum avalanche energy vs temperature 3 Test circuits Figure 19. Switching times test circuit for resistive load Figure 20. Gate charge test circuit Figure 21. Test circuit for inductive load switching and diode recovery times Figure 22. Unclamped Inductive load test circuit Figure 23. Unclamped inductive waveform Figure 24. Switching time waveform 4 Package mechanical data Table 10. TO-220FP mechanical data Figure 25. TO-220FP drawing 5 Packaging mechanical data 6 Revision history Table 11. Revision history
Electrical characteristics STB9NK90Z, STF9NK90Z, STP9NK90Z, STW9NK90Z 2 Electrical characteristics
(TCASE = 25 °C unless otherwise specified)
Table 5. On/off states Symbol Parameter Test conditions Min. Typ. Max. Unit
Drain-source breakdown V(BR)DSS I voltage D = 1 mA, VGS= 0 900 V Zero gate voltage drain V 1 µA I DS = max rating, DSS current (VGS = 0) VDS = max rating @125 °C 50 µA Gate body leakage current IGSS V (V GS = ± 20 V, VDS = 0 ±10 µA DS = 0) VGS(th) Gate threshold voltage VDS = VGS, ID = 100 µA 3 3.75 4.5 V Static drain-source on RDS(on) V resistance GS = 10 V, ID = 3.6 A 1.1 1.3 Ω
Table 6. Dynamic Symbol Parameter Test conditions Min. Typ. Max. Unit
Input capacitance Ciss 2115 pF Output capacitance V C DS = 25 V, f = 1 MHz, oss - 190 - pF Reverse transfer VGS = 0 Crss 40 pF capacitance Equivalent output C (1) oss eq V capacitance GS = 0, VDS = 0 to 720 V - 115 - pF Qg Total gate charge VDD = 720 V, ID = 8 A 72 nC Qgs Gate-source charge VGS =10 V - 14 - nC Q Figure 20 gd Gate-drain charge 38 nC 1. Coss eq. is defined as a constant equivalent capacitance giving the same charging time as Coss when VDS increases from 0 to 80% VDSS 4/17 Doc ID 9479 Rev 7 Document Outline Figure 1. Internal schematic diagram Table 1. Device summary 1 Electrical ratings Table 2. Absolute maximum ratings Table 3. Thermal data Table 4. Avalanche characteristics 2 Electrical characteristics Table 5. On/off states Table 6. Dynamic Table 7. Switching times Table 8. Source drain diode Table 9. Gate-source Zener diode 2.1 Electrical characteristics (curves) Figure 2. Safe operating area for TO-220, D·PAK Figure 3. Thermal impedance for TO-220, D·PAK Figure 4. Safe operating area for TO-220FP Figure 5. Thermal impedance for TO-220FP Figure 6. Safe operating area for TO-247 Figure 7. Thermal impedance for TO-247 Figure 8. Output characteristics Figure 9. Transfer characteristics Figure 10. Transconductance Figure 11. Static drain-source on resistance Figure 12. Gate charge vs gate-source voltage Figure 13. Capacitance variations Figure 14. Normalized gate threshold voltage vs temperature Figure 15. Normalized on resistance vs temperature Figure 16. Source-drain diode forward characteristics Figure 17. Normalized BVDSS vs temperature Figure 18. Maximum avalanche energy vs temperature 3 Test circuits Figure 19. Switching times test circuit for resistive load Figure 20. Gate charge test circuit Figure 21. Test circuit for inductive load switching and diode recovery times Figure 22. Unclamped Inductive load test circuit Figure 23. Unclamped inductive waveform Figure 24. Switching time waveform 4 Package mechanical data Table 10. TO-220FP mechanical data Figure 25. TO-220FP drawing 5 Packaging mechanical data 6 Revision history Table 11. Revision history