User Manual GD32E50x (GigaDevice) - 10

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14. Digital-to-analog converter (DAC) ... 316 14.1. Introduction ... 316 14.2. Main features ... 316 14.3. Function description .. 317
14.3.1. DAC enable ... 317 14.3.2. DAC output buffer ... 317 14.3.3. DAC data configuration ... 318 14.3.4. DAC trigger ... 318 14.3.5. DAC conversion .. 318 14.3.6. DAC output FIFO .. 319 14.3.7. DAC noise wave ... 319 14.3.8. DAC output voltage ... 320 14.3.9. DMA request ... 320 14.3.10. DAC concurrent conversion .. 320
14.4. DAC registers .. 321
14.4.1. Control register 0 (DAC_CTL0) .. 321 14.4.2. Software trigger register (DAC_SWT) .. 324 14.4.3. DAC_OUT0 12-bit right-aligned data holding register (OUT0_R12DH) ... 324 14.4.4. DAC_OUT0 12-bit left-aligned data holding register (OUT0_L12DH) .. 325 14.4.5. DAC_OUT0 8-bit right-aligned data holding register (OUT0_R8DH) ... 325 14.4.6. DAC_OUT1 12-bit right-aligned data holding register (OUT1_R12DH) ... 326 14.4.7. DAC_OUT1 12-bit left-aligned data holding register (OUT1_L12DH) .. 326 14.4.8. DAC_OUT1 8-bit right-aligned data holding register (OUT1_R8DH) ... 327 14.4.9. DAC concurrent mode 12-bit right-aligned data holding register (DACC_R12DH) .. 327 14.4.10. DAC concurrent mode 12-bit left-aligned data holding register (DACC_L12DH) ... 328 14.4.11. DAC concurrent mode 8-bit right-aligned data holding register (DACC_R8DH) .. 328 14.4.12. DAC_OUT0 data output register (OUT0_DO) .. 329 14.4.13. DAC_OUT1 data output register (OUT1_DO) .. 329 14.4.14. DAC Status register 0 (DAC_STAT0) ... 330 14.4.15. DAC Control Register 1 (DAC_CTL1) .. 330 14.4.16. DAC Status Register 1 (DAC_STAT1) .. 331
15. Comparator (CMP) .. 334 15.1. Overview .. 334 15.2. Characteristic .. 334 15.3. Function overview .. 334
10 Document Outline Table of Contents List of Figures List of Tables 1. System and memory architecture 1.1. Arm® Cortex®-M33 processor 1.2. System architecture 1.3. Memory map 1.3.1. Bit-banding 1.3.2. On-chip SRAM memory 1.3.3. On-chip flash memory overview 1.4. Boot configuration 1.5. Device electronic signature 1.5.1. Memory density information 1.5.2. Unique device ID (96 bits) 1.6. System configuration registers 2. Flash memory controller (FMC) 2.1. Overview 2.2. Characteristics 2.3. Function overview 2.3.1. Flash memory architecture 2.3.2. Read operations Wait state added: Current buffer: Pre-fetch buffer: IBUS cache: DBUS cache: 2.3.3. Unlock the FMC_CTL register 2.3.4. Page erase 2.3.5. Mass erase 2.3.6. Main flash programming 2.3.7. OTP programming 2.3.8. Option bytes erase 2.3.9. Option bytes modify 2.3.10. Option bytes description 2.3.11. Page erase / program protection 2.3.12. Security protection 2.4. Register definition 2.4.1. Wait state register (FMC_WS) 2.4.2. Unlock key register (FMC_KEY) 2.4.3. Option byte unlock key register (FMC_OBKEY) 2.4.4. Status register (FMC_STAT) 2.4.5. Control register (FMC_CTL) 2.4.6. Address register (FMC_ADDR) 2.4.7. Option byte status register (FMC_OBSTAT) 2.4.8. Erase/Program protection register (FMC_WP) 2.4.9. Product ID register (FMC_PID) 3. Backup registers (BKP) 3.1. Overview 3.2. Characteristics 3.3. Function overview 3.3.1. RTC clock calibration 3.3.2. Tamper detection 3.4. Register definition 3.4.1. Backup data register x (BKP_DATAx) (x= 0..41) 3.4.2. RTC signal output control register (BKP_OCTL) 3.4.3. Tamper pin control register (BKP_TPCTL) 3.4.4. Tamper control and status register (BKP_TPCS) 4. Power management unit (PMU) 4.1. Overview 4.2. Characteristics 4.3. Function overview 4.3.1. Battery backup domain 4.3.2. VDD/VDDA power domain VDD domain VDDA domain 4.3.3. 1.1V power domain High-driver mode 4.3.4. Power saving modes Sleep mode Deep-sleep mode Deep-sleep 1 mode Deep-sleep 2 mode Standby mode 4.4. Register definition 4.4.1. Control register 0 (PMU_CTL0) 4.4.2. Control and status register 0 (PMU_CS0) 4.4.3. Control register 1 (PMU_CTL1) 4.4.4. Control and status register 1 (PMU_CS1) 5. Reset and clock unit (RCU) High- and Extra-density Reset and clock control unit (RCU) 5.1. Reset control unit (RCTL) 5.1.1. Overview 5.1.2. Function overview Power reset System reset Backup domain reset 5.2. Clock control unit (CCTL) 5.2.1. Overview 5.2.2. Characteristics 5.2.3. Function overview High speed crystal oscillator (HXTAL) Internal 8M RC oscillators (IRC8M) Internal 48M RC oscillators (IRC48M) Phase locked loop (PLL) Low speed crystal oscillator (LXTAL) Internal 40K RC oscillator (IRC40K) System clock (CK_SYS) selection HXTAL clock monitor (CKM) Clock output capability Voltage control 5.3. Register definition 5.3.1. Control register (RCU_CTL) 5.3.2. Clock configuration register 0 (RCU_CFG0) 5.3.3. Clock interrupt register (RCU_INT) 5.3.4. APB2 reset register (RCU_APB2RST) 5.3.5. APB1 reset register (RCU_APB1RST) 5.3.6. AHB enable register (RCU_AHBEN) 5.3.7. APB2 enable register (RCU_APB2EN) 5.3.8. APB1 enable register (RCU_APB1EN) 5.3.9. Backup domain control register (RCU_BDCTL) 5.3.10. Reset source/clock register (RCU_RSTSCK) 5.3.11. AHB reset register (RCU_AHBRST) 5.3.12. Clock configuration register 1 (RCU_CFG1) 5.3.13. Deep-sleep mode voltage register (RCU_DSV) 5.3.14. Additional clock control register (RCU_ADDCTL) 5.3.15. Additional clock interrupt register (RCU_ADDINT) 5.3.16. PLL clock spread spectrum control register (RCU_PLLSSCTL) 5.3.17. Clock configuration register 2 (RCU_CFG2) 5.3.18. APB1 additional reset register (RCU_ADDAPB1RST) 5.3.19. APB1 additional enable register (RCU_ADDAPB1EN) Connectivity line devices: Reset and clock control unit (RCU) 5.4. Reset control unit (RCTL) 5.4.1. Overview 5.4.2. Function overview Power reset System reset Backup domain reset 5.5. Clock control unit (CCTL) 5.5.1. Overview 5.5.2. Characteristics 5.5.3. Function overview High speed crystal oscillator (HXTAL) Internal 8M RC oscillators (IRC8M) Internal 48M RC oscillators (IRC48M) Phase locked loop (PLL) Low speed crystal oscillator (LXTAL) Internal 40K RC oscillator (IRC40K) System clock (CK_SYS) selection HXTAL clock monitor (CKM) Clock output capability Voltage control 5.6. Register definition 5.6.1. Control register (RCU_CTL) 5.6.2. Clock configuration register 0 (RCU_CFG0) 5.6.3. Clock interrupt register (RCU_INT) 5.6.4. APB2 reset register (RCU_APB2RST) 5.6.5. APB1 reset register (RCU_APB1RST) 5.6.6. AHB enable register (RCU_AHBEN) 5.6.7. APB2 enable register (RCU_APB2EN) 5.6.8. APB1 enable register (RCU_APB1EN) 5.6.9. Backup domain control register (RCU_BDCTL) 5.6.10. Reset source/clock register (RCU_RSTSCK) 5.6.11. AHB reset register (RCU_AHBRST) 5.6.12. Clock configuration register 1 (RCU_CFG1) 5.6.13. Deep-sleep mode voltage register (RCU_DSV) 5.6.14. Additional clock control register (RCU_ADDCTL) 5.6.15. Additional Clock configuration register (RCU_ADDCFG) 5.6.16. Additional clock interrupt register (RCU_ADDINT) 5.6.17. PLL clock spread spectrum control register (RCU_PLLSSCTL) 5.6.18. Clock configuration register 2 (RCU_CFG2) 5.6.19. APB1 additional reset register (RCU_ADDAPB1RST) 5.6.20. APB1 additional enable register (RCU_ADDAPB1EN) 6. Clock trim controller (CTC) 6.1. Overview 6.2. Characteristics 6.3. Function overview 6.3.1. REF sync pulse generator 6.3.2. CTC trim counter 6.3.3. Frequency evaluation and automatically trim process 6.3.4. Software program guide 6.4. Register definition 6.4.1. Control register 0 (CTC_CTL0) 6.4.2. Control register 1 (CTC_CTL1) 6.4.3. Status register (CTC_STAT) 6.4.4. Interrupt clear register (CTC_INTC) 7. Interrupt/event controller (EXTI) 7.1. Overview 7.2. Characteristics 7.3. Interrupts function overview 7.4. External interrupt and event (EXTI) block diagram 7.5. External Interrupt and Event function overview 7.6. EXTI Register 7.6.1. Interrupt enable register (EXTI_INTEN) 7.6.2. Event enable register (EXTI_EVEN) 7.6.3. Rising edge trigger enable register (EXTI_RTEN) 7.6.4. Falling edge trigger enable register (EXTI_FTEN) 7.6.5. Software interrupt event register (EXTI_SWIEV) 7.6.6. Pending register (EXTI_PD) 8. General-purpose and alternate-function I/Os (GPIO and AFIO) 8.1. Overview 8.2. Characteristics 8.3. Function overview 8.3.1. GPIO pin configuration 8.3.2. External interrupt/event lines 8.3.3. Alternate functions (AF) 8.3.4. Input configuration 8.3.5. Output configuration 8.3.6. Analog configuration 8.3.7. Alternate function (AF) configuration 8.3.8. IO pin function selection GPIO: Alternate function: 8.3.9. GPIO locking function 8.3.10. GPIO I/O compensation cell 8.4. Remapping function I/O and debug configuration 8.4.1. Introduction 8.4.2. Main features 8.4.3. JTAG/SWD alternate function remapping 8.4.4. ADC AF remapping 8.4.5. TIMER AF remapping 8.4.6. USART AF remapping 8.4.7. I2C0 AF remapping 8.4.8. SPI0 AF remapping 8.4.9. SPI2/I2S2 AF remapping 8.4.10. CAN0 AF remapping 8.4.11. CAN1 AF remapping 8.4.12. Ethernet AF remapping 8.4.13. CTC AF remapping 8.4.14. CLK pins AF remapping 8.5. Register definition 8.5.1. Port control register 0 (GPIOx_CTL0, x=A..G) 8.5.2. Port control register 1 (GPIOx_CTL1, x=A..G) 8.5.3. Port input status register (GPIOx_ISTAT, x=A..G) 8.5.4. Port output control register (GPIOx_OCTL, x=A..G) 8.5.5. Port bit operate register (GPIOx_BOP, x=A..G) 8.5.6. Port bit clear register (GPIOx_BC, x=A..G) 8.5.7. Port configuration lock register (GPIOx_LOCK, x=A..G) 8.5.8. Port bit speed register (GPIOx_ SPD, x=A..G) 8.5.9. Event control register (AFIO_EC) 8.5.10. AFIO port configuration register 0 (AFIO_PCF0) 8.5.11. EXTI sources selection register 0 (AFIO_EXTISS0) 8.5.12. EXTI sources selection register 1 (AFIO_EXTISS1) 8.5.13. EXTI sources selection register 2 (AFIO_EXTISS2) 8.5.14. EXTI sources selection register 3 (AFIO_EXTISS3) 8.5.15. AFIO port configuration register 1 (AFIO_PCF1) 8.5.16. IO compensation control register (AFIO_CPSCTL) 8.5.17. AFIO port configuration register A (AFIO_PCFA) 8.5.18. AFIO port configuration register B (AFIO_PCFB) 8.5.19. AFIO port configuration register C (AFIO_PCFC) 8.5.20. AFIO port configuration register D (AFIO_PCFD) 8.5.21. AFIO port configuration register E (AFIO_PCFE) 8.5.22. AFIO port configuration register G (AFIO_PCFG) 9. CRC calculation unit (CRC) 9.1. Overview 9.2. Characteristics 9.3. Function overview 9.4. Register definition 9.4.1. Data register (CRC_DATA) 9.4.2. Free data register (CRC_FDATA) 9.4.3. Control register (CRC_CTL) 9.4.4. Initialization data register (CRC_IDATA) 9.4.5. Polynomial register (CRC_POLY) 10. Trigonometric Math Unit (TMU) 10.1. Overview 10.2. Characteristics 10.3. Function overview 10.3.1. TMU block diagram 10.3.2. Data format 10.3.3. Mode 0 description 10.3.4. Mode 1 description 10.3.5. Mode 2 description 10.3.6. Mode 3 description 10.3.7. Mode 4 description 10.3.8. Mode 5 description 10.3.9. Mode 6 description 10.3.10. Mode 7 description 10.3.11. Mode 8 description 10.4. Software guideline 10.5. TMU register 10.5.1. Input data0 register (TMU_IDATA0) 10.5.2. Input data1 register (TMU_IDATA1) 10.5.3. Control register (TMU_CTL) 10.5.4. Data0 register (TMU_DATA0) 10.5.5. Data1 register (TMU_DATA1) 10.5.6. Status register (TMU_STAT) 11. Direct memory access controller (DMA) 11.1. Overview 11.2. Characteristics 11.3. Block diagram 11.4. Function overview 11.4.1. DMA operation 11.4.2. Peripheral handshake 11.4.3. Arbitration 11.4.4. Address generation 11.4.5. Circular mode 11.4.6. Memory to memory mode 11.4.7. Channel configuration 11.4.8. Interrupt 11.4.9. DMA request mapping 11.5. Register definition 11.5.1. Interrupt flag register (DMA_INTF) 11.5.2. Interrupt flag clear register (DMA_INTC) 11.5.3. Channel x control register (DMA_CHxCTL) 11.5.4. Channel x counter register (DMA_CHxCNT) 11.5.5. Channel x peripheral base address register (DMA_CHxPADDR) 11.5.6. Channel x memory base address register (DMA_CHxMADDR) 12. Debug (DBG) 12.1. Introduction 12.2. JTAG/SW function description 12.2.1. Switch JTAG or SW interface 12.2.2. Pin assignment 12.2.3. JTAG daisy chained structure 12.2.4. Debug reset 12.2.5. JEDEC-106 ID code 12.3. Debug hold function description 12.3.1. Debug support for power saving mode 12.3.2. Debug support for TIMER, I2C, WWDGT, FWDGT and CAN 12.4. DBG registers 12.4.1. ID code register (DBG_ID) 12.4.2. Control register (DBG_CTL) 13. Analog-to-digital converter (ADC) 13.1. Introduction 13.2. Main features 13.3. Pins and internal signals 13.4. Functional description 13.4.1. Calibration (CLB) 13.4.2. ADC clock 13.4.3. ADCON switch 13.4.4. Single-ended and differential input channels 13.4.5. Regular and inserted channel groups 13.4.6. Conversion modes Single conversion mode Continuous conversion mode Scan conversion mode Discontinuous mode 13.4.7. Inserted channel management Auto-insertion Triggered insertion 13.4.8. Analog watchdog Analog watchdog 0 Analog watchdog 1/2 13.4.9. Data alignment 13.4.10. Programmable sample time 13.4.11. External trigger 13.4.12. DMA request 13.4.13. Temperature sensor, and internal reference voltage VREFINT 13.4.14. Programmable resolution (DRES) - fast conversion mode 13.4.15. On-chip hardware oversampling 13.5. ADC sync mode 13.5.1. Free mode 13.5.2. Regular parallel mode 13.5.3. Inserted parallel mode 13.5.4. Follow-up fast mode 13.5.5. Follow-up slow mode 13.5.6. Trigger rotation mode 13.5.7. Combined regular parallel & inserted parallel mode 13.5.8. Combined regular parallel & trigger rotation mode 13.5.9. Combined inserted parallel & follow-up mode 13.6. ADC interrupts 13.7. ADC registers 13.7.1. Status register (ADC_STAT) 13.7.2. Control register 0 (ADC_CTL0) 13.7.3. Control register 1 (ADC_CTL1) 13.7.4. Sample time register 0 (ADC_SAMPT0) 13.7.5. Sample time register 1 (ADC_SAMPT1) 13.7.6. Inserted channel data offset register x (ADC_IOFFx) (x=0..3) 13.7.7. Watchdog high threshold register 0 (ADC_WDHT0) 13.7.8. Watchdog low threshold register 0 (ADC_WDLT0) 13.7.9. Regular sequence register 0 (ADC_RSQ0) 13.7.10. Regular sequence register 1 (ADC_RSQ1) 13.7.11. Regular sequence register 2 (ADC_RSQ2) 13.7.12. Inserted sequence register (ADC_ISQ) 13.7.13. Inserted data register x (ADC_IDATAx) (x= 0..3) 13.7.14. Regular data register (ADC_RDATA) 13.7.15. Oversample control register (ADC_OVSAMPCTL) 13.7.16. Watchdog 1 Channel Selection Register (ADC_WD1SR) 13.7.17. Watchdog 2 Channel Selection Register (ADC_WD2SR) 13.7.18. Watchdog threshold register 1 (ADC_WDT1) 13.7.19. Watchdog threshold register 2 (ADC_WDT2) 13.7.20. Differential mode control register (ADC_DIFCTL) 14. Digital-to-analog converter (DAC) 14.1. Introduction 14.2. Main features 14.3. Function description 14.3.1. DAC enable 14.3.2. DAC output buffer 14.3.3. DAC data configuration 14.3.4. DAC trigger 14.3.5. DAC conversion 14.3.6. DAC output FIFO 14.3.7. DAC noise wave 14.3.8. DAC output voltage 14.3.9. DMA request 14.3.10. DAC concurrent conversion 14.4. DAC registers 14.4.1. Control register 0 (DAC_CTL0) 14.4.2. Software trigger register (DAC_SWT) 14.4.3. DAC_OUT0 12-bit right-aligned data holding register (OUT0_R12DH) 14.4.4. DAC_OUT0 12-bit left-aligned data holding register (OUT0_L12DH) 14.4.5. DAC_OUT0 8-bit right-aligned data holding register (OUT0_R8DH) 14.4.6. DAC_OUT1 12-bit right-aligned data holding register (OUT1_R12DH) 14.4.7. DAC_OUT1 12-bit left-aligned data holding register (OUT1_L12DH) 14.4.8. DAC_OUT1 8-bit right-aligned data holding register (OUT1_R8DH) 14.4.9. DAC concurrent mode 12-bit right-aligned data holding register (DACC_R12DH) 14.4.10. DAC concurrent mode 12-bit left-aligned data holding register (DACC_L12DH) 14.4.11. DAC concurrent mode 8-bit right-aligned data holding register (DACC_R8DH) 14.4.12. DAC_OUT0 data output register (OUT0_DO) 14.4.13. DAC_OUT1 data output register (OUT1_DO) 14.4.14. DAC Status register 0 (DAC_STAT0) 14.4.15. DAC Control Register 1 (DAC_CTL1) 14.4.16. DAC Status Register 1 (DAC_STAT1) 15. Comparator (CMP) 15.1. Overview 15.2. Characteristic 15.3. Function overview 15.3.1. CMP inputs and outputs 15.3.2. CMP output blanking 15.3.3. CMP register write protection 15.4. CMP registers 15.4.1. CMP1 Control/status register (CMP1_CS) 15.4.2. CMP3 Control/status register (CMP3_CS) 15.4.3. CMP5 Control/status register (CMP5_CS) 16. Watchdog timer (WDGT) 16.1. Free watchdog timer (FWDGT) 16.1.1. Overview 16.1.2. Characteristics 16.1.3. Function overview 16.1.4. Register definition Control register (FWDGT_CTL) Prescaler register (FWDGT_PSC) Reload register (FWDGT_RLD) Status register (FWDGT_STAT) 16.2. Window watchdog timer (WWDGT) 16.2.1. Overview 16.2.2. Characteristics 16.2.3. Function overview 16.2.4. Register definition Control register (WWDGT_CTL) Configuration register (WWDGT_CFG) Status register (WWDGT_STAT) 17. Real-time clock (RTC) 17.1. Overview 17.2. Characteristics 17.3. Function overview 17.3.1. RTC reset 17.3.2. RTC reading 17.3.3. RTC configuration 17.3.4. RTC flag assertion 17.4. RTC Register 17.4.1. RTC interrupt enable register (RTC_INTEN) 17.4.2. RTC control register (RTC_CTL) 17.4.3. RTC prescaler high register (RTC_PSCH) 17.4.4. RTC prescaler low register (RTC_PSCL) 17.4.5. RTC divider high register (RTC_DIVH) 17.4.6. RTC divider low register (RTC_DIVL) 17.4.7. RTC counter high register (RTC_CNTH) 17.4.8. RTC counter low register (RTC_CNTL) 17.4.9. RTC alarm high register (RTC_ALRMH) 17.4.10. RTC alarm low register (RTC_ALRML) 18. Timer (TIMERx) 18.1. Advanced timer (TIMERx, x=0, 7) 18.1.1. Overview 18.1.2. Characteristics 18.1.3. Block diagram 18.1.4. Function overview Clock selection Prescaler Up counting mode Down counting mode Center-aligned counting mode Counter repetition Capture/compare channels PWM mode Channel output reference signal Outputs complementary Dead time insertion Break function Quadrature decoder Hall sensor function Slave controller Single pulse mode Timers interconnection Timer DMA mode Timer debug mode 18.1.5. TIMERx registers(x=0, 7) Control register 0 (TIMERx_CTL0) Control register 1 (TIMERx_CTL1) Slave mode configuration register (TIMERx_SMCFG) DMA and interrupt enable register (TIMERx_DMAINTEN) Interrupt flag register (TIMERx_INTF) Software event generation register (TIMERx_SWEVG) Channel control register 0 (TIMERx_CHCTL0) Channel control register 1 (TIMERx_CHCTL1) Channel control register 2 (TIMERx_CHCTL2) Counter register (TIMERx_CNT) Prescaler register (TIMERx_PSC) Counter auto reload register (TIMERx_CAR) Counter repetition register (TIMERx_CREP) Channel 0 capture/compare value register (TIMERx_CH0CV) Channel 1 capture/compare value register (TIMERx_CH1CV) Channel 2 capture/compare value register (TIMERx_CH2CV) Channel 3 capture/compare value register (TIMERx_CH3CV) Complementary channel protection register (TIMERx_CCHP) DMA configuration register (TIMERx_DMACFG) DMA transfer buffer register (TIMERx_DMATB) Configuration register (TIMERx_CFG) 18.2. General level0 timer (TIMERx, x=1, 2, 3, 4) 18.2.1. Overview 18.2.2. Characteristics 18.2.3. Block diagram 18.2.4. Function overview Clock selection Prescaler Up counting mode Down counting mode Center-aligned counting mode Capture/compare channels PWM mode Channel output reference signal Quadrature decoder Hall sensor function Slave controller Single pulse mode Timers interconnection Timer DMA mode Timer debug mode 18.2.5. TIMERx registers(x=1, 2, 3, 4) Control register 0 (TIMERx_CTL0) Control register 1 (TIMERx_CTL1) Slave mode configuration register (TIMERx_SMCFG) DMA and interrupt enable register (TIMERx_DMAINTEN) Interrupt flag register (TIMERx_INTF) Software event generation register (TIMERx_SWEVG) Channel control register 0 (TIMERx_CHCTL0) Channel control register 1 (TIMERx_CHCTL1) Channel control register 2 (TIMERx_CHCTL2) Counter register (TIMERx_CNT) (x=1) Counter register (TIMERx_CNT) (x=2,3,4) Prescaler register (TIMERx_PSC) Counter auto reload register (TIMERx_CAR) (x=1) Counter auto reload register (TIMERx_CAR) (x=2,3,4) Channel 0 capture/compare value register (TIMERx_CH0CV) (x=1) Channel 0 capture/compare value register (TIMERx_CH0CV) (x=2,3,4) Channel 1 capture/compare value register (TIMERx_CH1CV) (x=1) Channel 1 capture/compare value register (TIMERx_CH1CV) (x=2,3,4) Channel 2 capture/compare value register (TIMERx_CH2CV) (x=1) Channel 2 capture/compare value register (TIMERx_CH2CV) (x=2,3,4) Channel 3 capture/compare value register (TIMERx_CH3CV) (x=1) Channel 3 capture/compare value register (TIMERx_CH3CV) (x=2,3,4) DMA configuration register (TIMERx_DMACFG) DMA transfer buffer register (TIMERx_DMATB)(x=1) DMA transfer buffer register (TIMERx_DMATB)(x=2,3,4) Configuration register (TIMERx_CFG) 18.3. General level1 timer (TIMERx, x=8, 11) 18.3.1. Overview 18.3.2. Characteristics 18.3.3. Block diagram 18.3.4. Function overview Clock selection Prescaler Up counting mode Capture/compare channels PWM mode Channel output reference signal Slave controller Single pulse mode Timers interconnection Timer debug mode 18.3.5. TIMERx registers(x=8, 11) Control register 0 (TIMERx_CTL0) Slave mode configuration register (TIMERx_SMCFG) Interrupt enable register (TIMERx_DMAINTEN) Interrupt flag register (TIMERx_INTF) Software event generation register (TIMERx_SWEVG) Channel control register 0 (TIMERx_CHCTL0) Channel control register 2 (TIMERx_CHCTL2) Counter register (TIMERx_CNT) Prescaler register (TIMERx_PSC) Counter auto reload register (TIMERx_CAR) Channel 0 capture/compare value register (TIMERx_CH0CV) Channel 1 capture/compare value register (TIMERx_CH1CV) Configuration register (TIMERx_CFG ) 18.4. General level2 timer (TIMERx, x=9, 10, 12, 13) 18.4.1. Overview 18.4.2. Characteristics 18.4.3. Block diagram 18.4.4. Function overview Clock selection Prescaler Up counting mode Capture/compare channels Channel output reference signal Timer debug mode 18.4.5. TIMERx registers(x=9, 10, 12, 13) Control register 0 (TIMERx_CTL0) Control register 1 (TIMERx_CTL1) Interrupt enable register (TIMERx_DMAINTEN) Interrupt flag register (TIMERx_INTF) Software event generation register (TIMERx_SWEVG) Channel control register 0 (TIMERx_CHCTL0) Channel control register 2 (TIMERx_CHCTL2) Counter register (TIMERx_CNT) Prescaler register (TIMERx_PSC) Counter auto reload register (TIMERx_CAR) Channel 0 capture/compare value register (TIMERx_CH0CV) Configuration register (TIMERx_CFG) 18.5. Basic timer (TIMERx, x=5, 6) 18.5.1. Overview 18.5.2. Characteristics 18.5.3. Block diagram 18.5.4. Function overview Clock selection Prescaler Up counting mode Timer debug mode 18.5.5. TIMERx registers(x=5, 6) Control register 0 (TIMERx_CTL0) Control register 1 (TIMERx_CTL1) Interrupt enable register (TIMERx_DMAINTEN) Interrupt flag register (TIMERx_INTF) Software event generation register (TIMERx_SWEVG) Counter register (TIMERx_CNT) Prescaler register (TIMERx_PSC) Counter auto reload register (TIMERx_CAR) 19. Super High-Resolution Timer (SHRTIMER) 19.1. Overview 19.2. Characteristics 19.3. Block diagram 19.4. Function overview 19.4.1. Master_TIMER unit Counter clock Up counting mode Repetition counter Counter reset Compare Half mode Synchronization input start/reset counter Update event and shadow registers DAC Trigger 19.4.2. Slave_TIMERx(x=0..4) unit Counter clock Up counting mode Repetition counter Counter reset Capure Compare Half mode Delayed mode Set/reset crossbar Output prepare signal Arbitration mechanism Output prepare signal: narrow pulses management Regular mode Dead-time mode Balanced mode IDLE control Delayed IDLE Balanced IDLE IDLE controlled by bunch mode Channel output stage Carrier-signal mode Synchronization input start/reset counter Update event and shadow registers External event filter Blanking mode Windowing mode DAC trigger 19.4.3. DLL calibrate 19.4.4. Bunch mode BM-counter counting mode Bunch mode timing Bunch mode entry Regular entry Delayed entry Bunch mode exit Counter clock in bunch mode Use SHRTIMER_STxCMP0CP register to emulate bunch mode 19.4.5. Synchronization input/output Synchronization output Synchronization input 19.4.6. External event 19.4.7. Fault input Fault channel System fault 19.4.8. Trigger to ADC 19.4.9. Trigger to DAC 19.4.10. Interrupt 19.4.11. DMA request 19.4.12. DMA mode 19.4.13. Debug mode SHRTIMER_HOLD = 0 SHRTIMER_HOLD = 1 19.5. Register definition 19.5.1. Master_TIMER registers SHRTIMER Master_TIMER control register 0 (SHRTIMER_MTCTL0) SHRTIMER Master_TIMER interrupt flag register (SHRTIMER_MTINTF) SHRTIMER Master_TIMER interrupt flag clear register (SHRTIMER_MTINTC) SHRTIMER Master_TIMER DMA and interrupt enable register (SHRTIMER_MTDMAINTEN) SHRTIMER Master_TIMER counter register (SHRTIMER_MTCNT) SHRTIMER Master_TIMER counter auto reload register (SHRTIMER_MTCAR) SHRTIMER Master_TIMER counter repetition register (SHRTIMER_MTCREP) SHRTIMER Master_TIMER compare 0 value register (SHRTIMER_MTCMP0V) SHRTIMER Master_TIMER compare 1 value register (SHRTIMER_MTCMP1V) SHRTIMER Master_TIMER compare 2 value register (SHRTIMER_MTCMP2V) SHRTIMER Master_TIMER compare 3 value register (SHRTIMER_MTCMP3V) SHRTIMER Master_TIMER additional control register (SHRTIMER_MTACTL) 19.5.2. Slave_TIMERx registers(x=0..4) SHRTIMER Slave_TIMERx control register 0 (SHRTIMER_STxCTL0) SHRTIMER Slave_TIMERx interrupt flag register (SHRTIMER_STxINTF) SHRTIMER Slave_TIMERx interrupt flag clear register (SHRTIMER_STxINTC) SHRTIMER Slave_TIMERx DMA and interrupt enable register (SHRTIMER_STxDMAINTEN) SHRTIMER Slave_TIMERx counter register (SHRTIMER_STxCNT) SHRTIMER Slave_TIMERx counter auto reload register (SHRTIMER_STxCAR) SHRTIMER Slave_TIMERx counter repetition register (SHRTIMER_STxCREP) SHRTIMER Slave_TIMERx compare 0 value register (SHRTIMER_STxCMP0V) SHRTIMER Slave_TIMERx compare 0 composite register (SHRTIMER_STxCMP0CP) SHRTIMER Slave_TIMERx compare 1 value register (SHRTIMER_STxCMP1V) SHRTIMER Slave_TIMERx compare 2 value register (SHRTIMER_STxCMP2V) SHRTIMER Slave_TIMERx compare 3 value register (SHRTIMER_STxCMP3V) SHRTIMER Slave_TIMERx capture 0 value register (SHRTIMER_STxCAP0V) SHRTIMER Slave_TIMERx capture 1 value register (SHRTIMER_STxCAP1V) SHRTIMER Slave_TIMERx dead-time control register (SHRTIMER_STxDTCTL) SHRTIMER Slave_TIMERx channel 0 set request register (SHRTIMER_STxCH0SET) SHRTIMER Slave_TIMERx channel 0 reset request register (SHRTIMER_STxCH0RST) SHRTIMER Slave_TIMERx channel 1 set request register (SHRTIMER_STxCH1SET) SHRTIMER Slave_TIMERx channel 1 reset request register (SHRTIMER_STxCH1RST) SHRTIMER Slave_TIMERx external event filter configuration register 0 (SHRTIMER_STxEXEVFCFG0) SHRTIMER Slave_TIMERx external event filter configuration register 1 (SHRTIMER_STxEXEVFCFG1) SHRTIMER Slave_TIMERx counter reset register (SHRTIMER_STxCNTRST) For Slave_TIMER0 For Slave_TIMER1 For Slave_TIMER2 For Slave_TIMER3 For Slave_TIMER4 SHRTIMER Slave_TIMERx carrier-signal control register (SHRTIMER_STxCSCTL) SHRTIMER Slave_TIMERx capture 0 trigger register (SHRTIMER_STxCAP0TRG) SHRTIMER Slave_TIMERx capture 1 trigger register (SHRTIMER_STxCAP1TRG) SHRTIMER Slave_TIMERx channel output control register (SHRTIMER_STxCHOCTL) SHRTIMER Slave_TIMERx fault control register (SHRTIMER_STxFLTCTL) SHRTIMER Slave_TIMERx additional control register (SHRTIMER_STxACTL) 19.5.3. Common registers SHRTIMER control register 0 (SHRTIMER_CTL0) SHRTIMER control register 1 (SHRTIMER_CTL1) SHRTIMER interrupt flag register (SHRTIMER_INTF) SHRTIMER interrupt flag clear register (SHRTIMER_INTC) SHRTIMER interrupt enable register (SHRTIMER_INTEN) SHRTIMER channel output enable register (SHRTIMER_CHOUTEN) SHRTIMER channel output disable register (SHRTIMER_CHOUTDIS) SHRTIMER channel output disable flag register (SHRTIMER_CHOUTDISF) SHRTIMER bunch mode control register (SHRTIMER_BMCTL) SHRTIMER bunch mode start trigger register (SHRTIMER_BMSTRG) SHRTIMER bunch mode compare value register (SHRTIMER_BMCMPV) SHRTIMER bunch mode counter auto reload register (SHRTIMER_BMCAR) SHRTIMER external event configuration register 0 (SHRTIMER_EXEVCFG0) SHRTIMER external event configuration register 1 (SHRTIMER_EXEVCFG1) SHRTIMER external event digital filter control register (SHRTIMER_EXEVDFCTL) SHRTIMER trigger source 0 to ADC register (SHRTIMER_ADCTRIGS0) SHRTIMER trigger source 1 to ADC register (SHRTIMER_ADCTRIGS1) SHRTIMER trigger source 2 to ADC register (SHRTIMER_ADCTRIGS2) SHRTIMER trigger source 3 to ADC register (SHRTIMER_ADCTRIGS3) SHRTIMER DLL calibration control register (SHRTIMER_DLLCCTL) SHRTIMER fault input configuration register 0 (SHRTIMER_FLTINCFG0) SHRTIMER fault input configuration register 1 (SHRTIMER_FLTINCFG1) SHRTIMER DMA update Master_TIMER register (SHRTIMER_DMAUPMTR) SHRTIMER DMA update Slave_TIMERx register (SHRTIMER_DMAUPSTxR)(x=0..4) SHRTIMER DMA transfer buffer register (SHRTIMER_DMATB) 20. Universal synchronous/asynchronous receiver /transmitter (USART) 20.1. Universal synchronous/asynchronous receiver /transmitter (USARTx, x=0..4) 20.1.1. Overview 20.1.2. Characteristics 20.1.3. Function overview USART frame format Baud rate generation USART transmitter USART receiver Use DMA for data buffer access Hardware flow control RTS flow control CTS flow control Multi-processor communication LIN mode Synchronous mode IrDA SIR ENDEC mode Half-duplex communication mode Smartcard (ISO7816-3) mode Character (T=0) mode Block (T=1) mode Direct and inverse convention USART interrupts 20.1.4. Register definition Status register 0 (USART_STAT0) Data register (USART_DATA) Baud rate register (USART_BAUD) Control register 0 (USART_CTL0) Control register 1 (USART_CTL1) Control register 2 (USART_CTL2) Guard time and prescaler register (USART_GP) Control register 3 (USART_CTL3) Receiver timeout register (USART_RT) Status register 1 (USART_STAT1) GD control register (USART_GDCTL) 20.2. Universal synchronous/asynchronous receiver /transmitter (USARTx, x=5) 20.2.1. Overview 20.2.2. Characteristics 20.2.3. Function overview USART frame format Baud rate generation USART transmitter USART receiver Use DMA for data buffer access Hardware flow control RTS flow control CTS flow control RS485 Driver Enable Multi-processor communication LIN mode Synchronous mode IrDA SIR ENDEC mode Half-duplex communication mode Smartcard (ISO7816-3) mode Character (T=0) mode Block (T=1) mode Direct and inverse convention Auto baudrate detection ModBus communication Receive FIFO Wakeup from power saving modes USART interrupts 20.2.4. Register defintion Control register 0 (USART_CTL0) Control register 1 (USART_CTL1) Control register 2 (USART_CTL2) Baud rate generator register (USART_BAUD) Prescaler and guard time configuration register (USART_GP) Receiver timeout register (USART_RT) Command register (USART_CMD) Status register (USART_STAT) Interrupt status clear register (USART_INTC) Receive data register (USART_RDATA) Transmit data register (USART_TDATA) USART coherence control register (USART_CHC) USART receive FIFO control and status register (USART_RFCS) 21. Inter-integrated circuit interface (I2C) 21.1. Inter-integrated circuit interface (I2Cx, x=0, 1) 21.1.1. Overview 21.1.2. Characteristics 21.1.3. Function overview SDA and SCL lines Data validation START and STOP condition Clock synchronization I2C communication flow Arbitration Programming model SCL line stretching Use DMA for data transfer Packet error checking SMBus support SAM_V support Status, errors and interrupts 21.1.4. Register definition Control register 0 (I2C_CTL0) Control register 1 (I2C_CTL1) Slave address register 0 (I2C_SADDR0) Slave address register 1 (I2C_SADDR1) Transfer buffer register (I2C_DATA) Transfer status register 0 (I2C_STAT0) Transfer status register 1 (I2C_STAT1) Clock configure register (I2C_CKCFG) Rise time register (I2C_RT) SAM control and status register (I2C_SAMCS) Control register 2 (I2C_CTL2) Control and status register (I2C_CS) Status clear register (I2C_STATC) 21.2. Inter-integrated circuit interface (I2Cx, x=2) 21.2.1. Overview 21.2.2. Characteristics 21.2.3. Function overview Clock requirements I2C communication flow Noise filter I2C timings Software reset Data transfer I2C slave mode I2C master mode SMBus support SMBus mode Wakeup from power saving modes Use DMA for data transfer I2C error and interrupts I2C debug mode 21.2.4. Register definition Control register 0 (I2C_CTL0) Control register 1 (I2C_CTL1) Slave address register 0 (I2C_SADDR0) Slave address register 1 (I2C_SADDR1) Timing register (I2C_TIMING) Timeout register (I2C_TIMEOUT) Status register (I2C_STAT) Status clear register (I2C_STATC) PEC register (I2C_PEC) Receive data register (I2C_RDATA) Transmit data register (I2C_TDATA) 22. Serial peripheral interface/Inter-IC sound (SPI/I2S) 22.1. Overview 22.2. Characteristics 22.2.1. SPI characteristics 22.2.2. I2S characteristics 22.3. SPI block diagram 22.4. SPI signal description 22.4.1. Normal configuration (Not Quad-SPI Mode) 22.4.2. Quad-SPI configuration 22.5. SPI function overview 22.5.1. SPI clock timing and data format 22.5.2. NSS function Slave Mode Master mode 22.5.3. SPI operation modes SPI initialization sequence SPI basic transmission and reception sequence Transmission sequence Reception sequence SPI operation sequence in different modes (Not Quad-SPI, TI mode or NSSP mode) SPI TI mode NSS pulse mode operation sequence Quad-SPI mode operation sequence Quad write operation Quad read operation SPI disabling sequence MFD SFD MTU MTB STU STB MRU MRB SRU SRB TI mode NSS pulse mode Quad-SPI mode 22.5.4. DMA function 22.5.5. CRC function 22.6. SPI interrupts 22.6.1. Status flags 22.6.2. Error conditions 22.7. I2S block diagram 22.8. I2S signal description 22.9. I2S function overview 22.9.1. I2S audio standards I2S Phillips standard MSB justified standard LSB justified standard PCM standard 22.9.2. I2S clock 22.9.3. Operation Operation modes I2S initialization sequence I2S master transmission sequence I2S master reception sequence I2S slave transmission sequence I2S slave reception sequence I2S full-duplex mode 22.9.4. DMA function 22.10. I2S interrupts 22.10.1. Status flags 22.10.2. Error conditions 22.11. Register definition 22.11.1. Control register 0 (SPI_CTL0) 22.11.2. Control register 1 (SPI_CTL1) 22.11.3. Status register (SPI_STAT) 22.11.4. Data register (SPI_DATA) 22.11.5. CRC polynomial register (SPI_CRCPOLY) 22.11.6. RX CRC register (SPI_RCRC) 22.11.7. TX CRC register (SPI_TCRC) 22.11.8. I2S control register (SPI_I2SCTL) 22.11.9. I2S clock prescaler register (SPI_I2SPSC) 22.11.10. Quad-SPI mode control register (SPI_QCTL) of SPI0 23. Serial/Quad Parallel Interface (SQPI) 23.1. Overview 23.2. Characteristics 23.3. Function overview 23.3.1. SQPI controller sampling polarity 23.3.2. SQPI controller special command 23.3.3. SQPI controller read ID command 23.3.4. SQPI controller output clock configuration 23.3.5. SQPI controller initialization 23.3.6. Read ID command flow 23.3.7. Read/Write operation flow 23.3.8. SQPI controller mode timing 23.4. Register definition 23.4.1. SQPI Initial Register (SQPI_INIT) 23.4.2. SQPI Read Command Register (SQPI_RCMD) 23.4.3. SQPI Write Command Register (SQPI_WCMD) 23.4.4. SQPI ID Low Register (SQPI_IDL) 23.4.5. SQPI ID High Register (SQPI_IDH) 24. Secure digital input/output interface (SDIO) 24.1. Introduction 24.2. Main features 24.3. SDIO bus topology 24.4. SDIO functional description 24.4.1. SDIO adapter Control unit Command unit Command state machine Data unit Data state machine 24.4.2. AHB interface Register unit Data FIFO 24.5. Card functional description 24.5.1. Card registers 24.5.2. Commands Commands types Command format Command classes Detailed command description 24.5.3. Responses Responses types Responses format R1 (normal response command) R1b R2 (CID, CSD register) R3 (OCR register) R4 (Fast I/O) R4b R5 (Interrupt request) R5b R6 (Published RCA response) R7 (Card interface condition) 24.5.4. Data packets format 1-bit data packet format 4-bit data packet format 8-bit data packet format 24.5.5. Two status fields of the card Card status SD status register 24.6. Programming sequence 24.6.1. Card identification Card reset Operating voltage range validation Card identification process 24.6.2. No data commands 24.6.3. Single block or multiple block write 24.6.4. Single block or multiple block read 24.6.5. Stream write and stream read (MMC only) Stream write Stream read 24.6.6. Erase 24.6.7. Bus width selection 24.6.8. Protection management 24.6.9. Card Lock/Unlock operation 24.7. Specific operations 24.7.1. SD I/O specific operations 24.7.2. CE-ATA specific operations 24.8. SDIO registers 24.8.1. Power control register (SDIO_PWRCTL) 24.8.2. Clock control register (SDIO_CLKCTL) 24.8.3. Command argument register (SDIO_CMDAGMT) 24.8.4. Command control register (SDIO_CMDCTL) 24.8.5. Command index response register (SDIO_RSPCMDIDX) 24.8.6. Response register (SDIO_RESPx x=0..3) 24.8.7. Data timeout register (SDIO_DATATO) 24.8.8. Data length register (SDIO_DATALEN) 24.8.9. Data control register (SDIO_DATACTL) 24.8.10. Data counter register (SDIO_DATACNT) 24.8.11. Status register (SDIO_STAT) 24.8.12. Interrupt clear register (SDIO_INTC) 24.8.13. Interrupt enable register (SDIO_INTEN) 24.8.14. FIFO counter register (SDIO_FIFOCNT) 24.8.15. FIFO data register (SDIO_FIFO) 25. External memory controller (EXMC) 25.1. Overview 25.2. Characteristics 25.3. Function overview 25.3.1. Block diagram 25.3.2. Basic regulation of EXMC access 25.3.3. External device address mapping NOR/PSRAM address mapping NAND/PC Card address mapping NAND address mapping 25.3.4. NOR/PSRAM controller NOR/PSRAM memory device interface description Supported memory access mode NOR Flash/PSRAM controller timing Asynchronous access timing diagram Synchronous access timing diagram 25.3.5. NAND Flash or PC Card controller NAND Flash or PC Card interface function Supported memory access mode NAND Flash or PC Card controller timing NAND Flash operation NAND Flash pre-wait functionality NAND Flash ECC calculation module PC/CF Card access 25.4. Registers definition 25.4.1. NOR/PSRAM controller registers SRAM/NOR Flash control registers (EXMC_SNCTLx) (x=0, 1, 2, 3) SRAM/NOR Flash timing configuration registers (EXMC_SNTCFGx) (x=0, 1, 2, 3) SRAM/NOR Flash write timing configuration registers (EXMC_SNWTCFGx) (x=0, 1, 2, 3) 25.4.2. NAND Flash/PC Card controller registers NAND Flash/PC Card control registers (EXMC_NPCTLx) (x=1, 2, 3) NAND Flash/PC Card interrupt enable registers (EXMC_NPINTENx) (x=1, 2, 3) NAND Flash/PC Card common space timing configuration registers (EXMC_NPCTCFGx) (x=1, 2, 3) NAND Flash/PC Card attribute space timing configuration registers (EXMC_NPATCFGx) (x=1, 2, 3) PC Card I/O space timing configuration register (EXMC_PIOTCFG3) NAND Flash ECC registers (EXMC_NECCx) (x=1, 2) 26. Controller area network (CAN) 26.1. Overview 26.2. Characteristics 26.3. Function overview 26.3.1. Working mode Sleep working mode Initial working mode Normal working mode 26.3.2. Communication modes Silent communication mode Loopback communication mode Loopback and silent communication mode Normal communication mode 26.3.3. Data transmission Transmission register Transmit mailbox state Transmit status and error Steps of sending a frame Transmission options 26.3.4. Data reception Reception register Rx FIFO Rx FIFO status Steps of receiving a message 26.3.5. Filtering function Scale Mask mode List mode Filter number Associated FIFO Active Filtering index Priority 26.3.6. Time-triggered communication 26.3.7. Communication parameters Automatic retransmission forbid mode Bit time Baud rate 26.3.8. CAN FD operation 26.3.9. Transmitter Delay Compensation 26.3.10. Error flags Bus-Off recovery 26.3.11. CAN interrupts Transmit interrupt Receive FIFO0 interrupt Rx FIFO1 interrupt Error and working mode change interrupt 26.4. CAN registers 26.4.1. Control register (CAN_CTL) 26.4.2. Status register (CAN_STAT) 26.4.3. Transmit status register (CAN_TSTAT) 26.4.4. Receive message FIFO0 register (CAN_RFIFO0) 26.4.5. Receive message FIFO1 register (CAN_RFIFO1) 26.4.6. Interrupt enable register (CAN_INTEN) 26.4.7. Error register (CAN_ERR) 26.4.8. Bit timing register (CAN_BT) 26.4.9. FD control register (CAN_FDCTL) 26.4.10. FD status register (CAN_FDSTAT) 26.4.11. FD transmitter delay compensation register (CAN_FDTDC) 26.4.12. Date Bit timing register (CAN_DBT) 26.4.13. Transmit mailbox identifier register (CAN_TMIx) (x=0..2) 26.4.14. Transmit mailbox property register (CAN_TMPx) (x=0..2) 26.4.15. Transmit mailbox data0 register (CAN_TMDATA0x) (x=0..2) 26.4.16. Transmit mailbox data1 register (CAN_TMDATA1x) (x=0..2) 26.4.17. Receive FIFO mailbox identifier register (CAN_RFIFOMIx) (x=0,1) 26.4.18. Receive FIFO mailbox property register (CAN_RFIFOMPx) (x=0,1) 26.4.19. Receive FIFO mailbox data0 register (CAN_RFIFOMDATA0x) (x=0,1) 26.4.20. Receive FIFO mailbox data1 register (CAN_RFIFOMDATA1x) (x=0,1) 26.4.21. Filter control register (CAN_FCTL) 26.4.22. Filter mode configuration register (CAN_FMCFG) 26.4.23. Filter scale configuration register (CAN_FSCFG) 26.4.24. Filter associated FIFO register (CAN_FAFIFO) 26.4.25. Filter working register (CAN_FW) 26.4.26. Filter x data y register (CAN_FxDATAy) (x=0..27, y=0,1) 27. Ethernet (ENET) 27.1. Overview 27.2. Characteristics 27.2.1. Block diagram 27.2.2. MAC 802.3 Ethernet packet description 27.2.3. Ethernet signal description 27.3. Function overview 27.3.1. Interface configuration SMI: Station management interface SMI write operation SMI read operation SMI clock selection MII/RMII selection MII: Media independent interface MII clock sources RMII: Reduced media independent interface MII/RMII bit transmission order RMII clock sources 27.3.2. MAC function overview Transmission process of MAC Handle special cases Transmission management of MAC Jabber timer Collision condition solve mechanism – Re-transmission Transmit status word Transmit FIFO flush operation Transmit flow control Transmit inter-frame gap management Transmit checksum offload MAC receive filters Address filtering Unicast frame destination address filter Multicast frame destination address filter Hash or perfect address filter Broadcast frame destination address filter Unicast frame source address filter Reverse filtering operation Promiscuous mode Pause control frame filter Reception process of MAC Reception management of MAC Receive operation on multi-frame handling Receive flow control Receive checksum offload Error handling Receive status word MAC loopback mode 27.3.3. MAC statistics counters: MSC 27.3.4. Wake up management: WUM Remote wakeup frame detection Remote wakeup frame filter register Magic packet detection Precautions during system power-down state 27.3.5. Precision time protocol: PTP Reference clock source Synchronization accuracy System time correction method System time initialization procedure System time update steps under coarse correction method System time update steps under fine correction method Transmission and reception of frames with the PTP feature PTP trigger internal connection with TIMER1 PTP pulse-per-second (PPS) output signal 27.3.6. DMA controller description Alignment rule for data buffer address The effective length of the buffer Arbitration for TxDMA and RxDMA controller Error response to DMA controller DMA controller initialization for transmission and reception TxDMA configuration Operate on second frame in buffer TxDMA operation mode (A) (default mode): Non-OSF TxDMA operation mode (B): OSF Transmit frame format in buffer Transmit frame processing Suspend during transmit polling Transmit DMA descriptor with IEEE 1588 timestamp format TxDMA descriptors in normal mode TxDMA descriptors in enhanced mode RxDMA configuration Receive descriptor fetching regulation Process of receiving frame Processing after a new frame received in suspend state Receive DMA descriptor with IEEE 1588 timestamp format RxDMA descriptors in normal mode RxDMA descriptors in enhanced mode 27.3.7. Example for a typical configuration flow of Ethernet 27.3.8. Ethernet interrupts MAC interrupts DMA controller interrupts 27.4. Register definition 27.4.1. MAC configuration register (ENET_MAC_CFG) 27.4.2. MAC frame filter register (ENET_MAC_FRMF) 27.4.3. MAC hash list high register (ENET_MAC_HLH) 27.4.4. MAC hash list low register (ENET_MAC_HLL) 27.4.5. MAC PHY control register (ENET_MAC_PHY_CTL) 27.4.6. MAC MII data register (ENET_MAC_PHY_DATA) 27.4.7. MAC flow control register (ENET_MAC_FCTL) 27.4.8. MAC VLAN tag register (ENET_MAC_VLT) 27.4.9. MAC remote wakeup frame filter register (ENET_MAC_RWFF) 27.4.10. MAC wakeup management register (ENET_MAC_WUM) 27.4.11. MAC debug register (ENET_MAC_DBG) 27.4.12. MAC interrupt flag register (ENET_MAC_INTF) 27.4.13. MAC interrupt mask register (ENET_MAC_INTMSK) 27.4.14. MAC address 0 high register (ENET_MAC_ADDR0H) 27.4.15. MAC address 0 low register (ENET_MAC_ADDR0L) 27.4.16. MAC address 1 high register (ENET_MAC_ADDR1H) 27.4.17. MAC address 1 low register (ENET_MAC_ADDR1L) 27.4.18. MAC address 2 high register (ENET_MAC_ADDR2H) 27.4.19. MAC address 2 low register (ENET_MAC_ADDR2L) 27.4.20. MAC address 3 high register (ENET_MAC_ADDR3H) 27.4.21. MAC address 3 low register (ENET_MAC_ADDR3L) 27.4.22. MAC flow control threshold register (ENET_MAC_FCTH) 27.4.23. MSC control register (ENET_MSC_CTL) 27.4.24. MSC receive interrupt flag register (ENET_MSC_RINTF) 27.4.25. MSC transmit interrupt flag register (ENET_MSC_TINTF) 27.4.26. MSC receive interrupt mask register (ENET_MSC_RINTMSK) 27.4.27. MSC transmit interrupt mask register (ENET_MSC_TINTMSK) 27.4.28. MSC transmitted good frames after a single collision counter register (ENET_MSC_SCCNT) 27.4.29. MSC transmitted good frames after more than a single collision counter register (ENET_MSC_MSCCNT) 27.4.30. MSC transmitted good frames counter register (ENET_MSC_TGFCNT) 27.4.31. MSC received frames with CRC error counter register (ENET_MSC_RFCECNT) 27.4.32. MSC received frames with alignment error counter register (ENET_MSC_RFAECNT) 27.4.33. MSC received good unicast frames counter register (ENET_MSC_RGUFCNT) 27.4.34. PTP time stamp control register (ENET_PTP_TSCTL) 27.4.35. PTP subsecond increment register (ENET_PTP_SSINC) 27.4.36. PTP time stamp high register (ENET_PTP_TSH) 27.4.37. PTP time stamp low register (ENET_PTP_TSL) 27.4.38. PTP time stamp update high register (ENET_PTP_TSUH) 27.4.39. PTP time stamp update low register (ENET_PTP_TSUL) 27.4.40. PTP time stamp addend register (ENET_PTP_TSADDEND) 27.4.41. PTP expected time high register (ENET_PTP_ETH) 27.4.42. PTP expected time low register (ENET_PTP_ETL) 27.4.43. PTP time stamp flag register (ENET_PTP_TSF) 27.4.44. PTP PPS control register (ENET_PTP_PPSCTL) 27.4.45. DMA bus control register (ENET_DMA_BCTL) 27.4.46. DMA transmit poll enable register (ENET_DMA_TPEN) 27.4.47. DMA receive poll enable register (ENET_DMA_RPEN) 27.4.48. DMA receive descriptor table address register (ENET_DMA_RDTADDR) 27.4.49. DMA transmit descriptor table address register (ENET_DMA_TDTADDR) 27.4.50. DMA status register (ENET_DMA_STAT) 27.4.51. DMA control register (ENET_DMA_CTL) 27.4.52. DMA interrupt enable register (ENET_DMA_INTEN) 27.4.53. DMA missed frame and buffer overflow counter register (ENET_DMA_MFBOCNT) 27.4.54. DMA receive state watchdog counter register (ENET_DMA_RSWDC) 27.4.55. DMA current transmit descriptor address register (ENET_DMA_CTDADDR) 27.4.56. DMA current receive descriptor address register (ENET_DMA_CRDADDR) 27.4.57. DMA current transmit buffer address register (ENET_DMA_CTBADDR) 27.4.58. DMA current receive buffer address register (ENET_DMA_CRBADDR) 28. Universal Serial Bus full-speed device interface (USBD) 28.1. Overview 28.2. Main features 28.3. Block diagram 28.4. Signal description 28.5. Clock configuration 28.6. Function overview 28.6.1. USB endpoints Endpoint buffer Endpoint buffer descriptor table Double-buffered endpoints Endpoint memory requests arbitration 28.6.2. Operation procedure USB transaction process IN transaction OUT and SETUP transaction Control transfers Isochronous transfers 28.6.3. USB events and interrupts Reset events Suspend and resume events Link Power Management (LPM) level L1 USB Interrupts 28.6.4. Operation guide USBD register initialization sequence Endpoint initialization sequence SETUP and OUT data transfers IN data transfers 28.7. Registers definition 28.7.1. USBD control register (USBD_CTL) 28.7.2. USBD interrupt flag register (USBD_INTF) 28.7.3. USBD status register (USBD_STAT) 28.7.4. USBD device address register (USBD_DADDR) 28.7.5. USBD buffer address register (USBD_BADDR) 28.7.6. USBD endpoint x control and status register (USBD_EPxCS), x=[0..7] 28.7.7. USBD endpoint x transmission buffer address register (USBD_EPxTBADDR), x can be in [0..7] 28.7.8. USBD endpoint x transmission buffer byte count register (USBD_EPxTBCNT), x can be in [0..7] 28.7.9. USBD endpoint x reception buffer address register (USBD_EPxRBADDR), x can be in [0..7] 28.7.10. USBD endpoint x reception buffer byte count register (USBD_EPxRBCNT), x can be in [0..7] 28.7.11. USBD LPM control and status register (USBD_LPMCS) 29. Universal serial bus High-Speed interface (USBHS) 29.1. Overview 29.2. Characteristics 29.3. Block diagram 29.4. Signal description 29.5. Function overview 29.5.1. USBHS PHY selection, clocks and working modes 29.5.2. USB host function 29.5.3. USB device function 29.5.4. OTG function overview 29.5.5. Data FIFO 29.5.6. DMA function 29.5.7. Operation guide Host mode Device mode 29.6. Interrupts 29.7. Register definition 29.7.1. USBHS global registers Global OTG control and status register (USBHS_GOTGCS) Global OTG interrupt flag register (USBHS_GOTGINTF) Global AHB control and status register (USBHS_GAHBCS) Global USB control and status register (USBHS_GUSBCS) Global reset control register (USBHS_GRSTCTL) Global interrupt flag register (USBHS_GINTF) Global interrupt enable register (USBHS_GINTEN) Global receive status read/receive status read and pop registers (USBHS_GRSTATR/USBHS_GRSTATP) Global receive FIFO length register (USBHS_GRFLEN) Host non-periodic transmit FIFO length register /Device IN endpoint 0 transmit FIFO length (USBHS_HNPTFLEN _DIEP0TFLEN) Host non-periodic transmit FIFO/queue status register (USBHS_HNPTFQSTAT) Global core configuration register (USBHS_GCCFG) Core ID register (USBHS_CID) Global core LPM configuration register (USBHS_GLPMCFG) Power down register (USBHS_PWRD) ADP control and status register (USBHS_ADPCTL) Host periodic transmit FIFO length register (USBHS_HPTFLEN) Device IN endpoint transmit FIFO length register (USBHS_DIEPxTFLEN) (x = 1..5, where x is the FIFO_number) 29.7.2. Host control and status registers Host control register (USBHS_HCTL) Host frame interval register (USBHS_HFT) Host frame information remaining register (USBHS_HFINFR) Host periodic transmit FIFO/queue status register (USBHS_HPTFQSTAT) Host all channels interrupt register (USBHS_HACHINT) Host all channels interrupt enable register (USBHS_HACHINTEN) Host port control and status register (USBHS_HPCS) Host channel-x control register (USBHS_HCHxCTL) (x = 0..11, where x = channel_number) Host channel-x interrupt flag register (USBHS_HCHxINTF) (x = 0..11, where x = channel number) Host channel-x interrupt enable register (USBHS_HCHxINTEN) (x = 0..11, where x = channel number) Host channel-x transfer length register (USBHS_HCHxLEN) (x = 0..11, where x = channel number) Host channel-x DMA address register (USBHS_HCHxDMAADDR) (x = 0..11, where x = channel number) 29.7.3. Device control and status registers Device configuration register (USBHS_DCFG) Device control register (USBHS_DCTL) Device status register (USBHS_DSTAT) Device IN endpoint common interrupt enable register (USBHS_DIEPINTEN) Device OUT endpoint common interrupt enable register (USBHS_DOEPINTEN) Device all endpoints interrupt register (USBHS_DAEPINT) Device all endpoints interrupt enable register (USBHS_DAEPINTEN) Device VBUS discharge time register (USBHS_DVBUSDT) Device VBUS pulsing time register (USBHS_DVBUSPT) Device IN endpoint FIFO empty interrupt enable register (USBHS_DIEPFEINTEN) Device endpoint 1 interrupt register (USBHS_DEP1INT) Device endpoint 1 interrupt enable register (USBHS_DEP1INTEN) Device IN endpoint-1 interrupt enable register (USBHS_DIEP1INTEN) Device OUT endpoint-1 interrupt enable register (USBHS_DOEP1INTEN) Device IN endpoint 0 control register (USBHS_DIEP0CTL) Device IN endpoint-x control register (USBHS_DIEPxCTL) (x = 1..5, where x = endpoint_number) Device OUT endpoint 0 control register (USBHS_DOEP0CTL) Device OUT endpoint-x control register (USBHS_DOEPxCTL) (x = 1..5, where x = endpoint_number) Device IN endpoint-x interrupt flag register (USBHS_DIEPxINTF) (x = 0..5, where x = endpoint_number) Device OUT endpoint-x interrupt flag register (USBHS_DOEPxINTF) (x = 0..5, where x = endpoint_number) Device IN endpoint 0 transfer length register (USBHS_DIEP0LEN) Device OUT endpoint 0 transfer length register (USBHS_DOEP0LEN) Device IN endpoint-x transfer length register (USBHS_DIEPxLEN) (x = 1..5, where x = endpoint_number) Device OUT endpoint-x transfer length register (USBHS_DOEPxLEN) (x = 1..5, where x = endpoint_number) Device IN endpoint-x DMA address register (USBHS_DIEPxDMAADDR) / Device OUT endpoint-x DMA address register (USBHS_DOEPxDMAADDR) (x = 0..5, where x = endpoint_number) Device IN endpoint-x transmit FIFO status register (USBHS_DIEPxTFSTAT) (x = 0..5, where x = endpoint_number) 29.7.4. Power and clock control register (USBHS_PWRCLKCTL) 30. Revision history