Datasheet STM32L552xx (STMicroelectronics) - 304

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Electrical characteristics STM32L552xx Delay block
Unless otherwise specified, the parameters given in Table 149 for delay block are derived from tests performed under the ambient temperature, fPCLKx frequency and VDD supply voltage conditions summarized in Table 27: General operating conditions with the configuration shown in the figure below.
Table 149. Dynamics characteristics: delay block characteristics Symbol Parameter Conditions Min Typ Max Unit
tinit Initial delay - 1175 1375 1450 ps t∆ Unit delay - 250 500 750
5.3.32 SD/SDIO/MMC card host interfaces (SDMMC)
Unless otherwise specified, the parameters given in Table 150 and Table 151 for SDIO are derived from tests performed under the ambient temperature, fPCLKx frequency and VDD supply voltage conditions summarized in Table 27: General operating conditions with the following configuration: • Output speed is set to OSPEEDRy[1:0] = 11 • Capacitive load C = 30 pF • Measurement points are done at CMOS levels: 0.5VDD Refer to Section 5.3.15: I/O port characteristics for more details on the input/output characteristics.
Table 150. Dynamics characteristics: SD / eMMC characteristics, VDD=2.7V to 3.6 V(1) Symbol Parameter Conditions Min Typ Max Unit
Clock frequency in data transfer fPP - 0 - 70 MHz mode - SDIO_CK/fPCLK2 frequency ratio - - - 8/3 - tW(CKL) Clock low time fpp =52MHz 8.5 9.5 - ns tW(CKH) Clock high time fpp =52MHz 8.5 9.5 -
CMD, D inputs (referenced to CK) in eMMC legacy/SDR/DDR and SD HS/SDR(2)/DDR(2) mode
tISU Input setup time HS - 2.5 - - ns tIHD Input hold time HS - 1 - -
CMD, D outputs (referenced to CK) in eMMC legacy/SDR/DDR and SD HS/SDR(2) /DDR(2) mode
tOV Output valid time HS - - 5 6 ns tOH Output hold time HS - 4.5 - -
CMD, D inputs (referenced to CK) in SD default mode
tISUD Input setup time SD - 2.5 - - ns tIHD Input hold time SD - 1 - - 304/340 DS12737 Rev 6 Document Outline Table 1. Device summary 1 Introduction 2 Description Table 2. STM32L552xx features and peripheral counts (continued) Figure 1. STM32L552xx block diagram 3 Functional overview 3.1 Arm® Cortex®-M33 core with TrustZone® and FPU 3.2 Art Accelerator – instruction cache (ICACHE) 3.3 Memory protection unit 3.4 Embedded Flash memory 3.5 Embedded SRAM 3.6 Boot modes Table 3. Boot modes when TrustZone is disabled (TZEN=0) Table 4. Boot modes when TrustZone is enabled (TZEN=1) Table 5. Boot space versus RDP protection (continued) 3.7 Global TrustZone controller (GTZC) 3.8 TrustZone security architecture Table 6. Example of memory map security attribution vs SAU configuration regions 3.8.1 TrustZone peripheral classification Table 7. Securable peripherals by TZSC (continued) Table 8. TrustZone-aware peripherals 3.9 Power supply management 3.9.1 Power supply schemes Figure 2. STM32L552xx power supply overview Figure 3. STM32L552xxxxP power supply overview Figure 4. STM32L552xxxxQ power supply overview Figure 5. Power-up/down sequence 3.9.2 Power supply supervisor 3.9.3 Voltage regulator 3.9.4 SMPS step down converter Figure 6. SMPS step down converter power supply scheme Table 9. SMPS external components 3.9.5 Low-power modes Table 10. STM32L552xx modes overview (continued) Table 11. Functionalities depending on the working mode (continued) 3.9.6 Reset mode 3.9.7 VBAT operation 3.9.8 PWR TrustZone security 3.10 Peripheral interconnect matrix Table 12. STM32L552xx peripherals interconnect matrix (continued) 3.11 Reset and clock controller (RCC) Figure 7. STM32L552xx clock tree 3.12 Clock recovery system (CRS) 3.13 General-purpose inputs/outputs (GPIOs) 3.14 Multi-AHB bus matrix Figure 8. Multi-AHB bus matrix 3.15 Direct memory access controller (DMA) Table 13. DMA1 and DMA2 implementation 3.16 DMA request router (DMAMUX) 3.17 Interrupts and events 3.17.1 Nested vectored interrupt controller (NVIC) 3.17.2 Extended interrupt/event controller (EXTI) 3.18 Cyclic redundancy check calculation unit (CRC) 3.19 Flexible static memory controller (FSMC) 3.20 Octo-SPI interface (OCTOSPI) 3.21 Analog-to-digital converter (ADC) 3.21.1 Temperature sensor Table 14. Temperature sensor calibration values 3.21.2 Internal voltage reference (VREFINT) Table 15. Internal voltage reference calibration values 3.21.3 VBAT battery voltage monitoring 3.22 Digital to analog converter (DAC) 3.23 Voltage reference buffer (VREFBUF) Figure 9. Voltage reference buffer 3.24 Comparators (COMP) 3.25 Operational amplifier (OPAMP) 3.26 Digital filter for sigma-delta modulators (DFSDM) 3.27 Touch sensing controller (TSC) 3.28 True random number generator (RNG) 3.29 HASH hardware accelerator (HASH) 3.30 Timers and watchdogs Table 16. Timer feature comparison 3.30.1 Advanced-control timer (TIM1, TIM8) 3.30.2 General-purpose timers (TIM2, TIM3, TIM4, TIM5, TIM15, TIM16, TIM17) 3.30.3 Basic timers (TIM6 and TIM7) 3.30.4 Low-power timers (LPTIM1, LPTIM2 and LPTIM3) 3.30.5 Independent watchdog (IWDG) 3.30.6 Window watchdog (WWDG) 3.30.7 SysTick timer 3.31 Real-time clock (RTC) 3.32 Tamper and backup registers (TAMP) 3.33 Inter-integrated circuit interface (I2C) Table 17. I2C implementation 3.34 Universal synchronous/asynchronous receiver transmitter (USART) Table 18. USART/UART/LPUART features 3.35 Low-power universal asynchronous receiver transmitter (LPUART) 3.36 Serial peripheral interface (SPI) 3.37 Serial audio interfaces (SAI) Table 19. SAI implementation 3.38 Secure digital input/output and MultiMediaCards Interface (SDMMC) 3.39 Controller area network (FDCAN) 3.40 Universal serial bus (USB FS) 3.41 USB Type-C™ / USB Power Delivery controller (UCPD) 3.42 Development support 3.42.1 Serial wire JTAG debug port (SWJ-DP) 3.42.2 Embedded Trace Macrocell™ 4 Pinouts and pin description Figure 10. STM32L552xx LQFP48 pinout Figure 11. STM32L552xxxxP LQFP48 external SMPS pinout Figure 12. STM32L552xx UFQFPN48 pinout Figure 13. STM32L552xxxxP UFQFPN48 external SMPS pinout Figure 14. STM32L552xx LQFP64 pinout Figure 15. STM32L552xxxxQ LQFP64 SMPS step down converter pinout Figure 16. STM32L552xxxxP LQFP64 external SMPS pinout Figure 17. STM32L552xxxxQ WLCSP81 SMPS step down converter ballout Figure 18. STM32L552xxxxP WLCSP81 external SMPS ballout Figure 19. STM32L552xx LQFP100 pinout Figure 20. STM32L552xxxxQ LQFP100 SMPS step down converter pinout Figure 21. STM32L552xx UFBGA132 ballout Figure 22. STM32L552xxxxQ UFBGA132 SMPS step down converter ballout Figure 23. STM32L552xx LQFP144 pinout Figure 24. STM32L552xxxxQ LQFP144 SMPS step down converter pinout Table 20. Legend/abbreviations used in the pinout table Table 21. STM32L552xx pin definitions (continued) Table 22. Alternate function AF0 to AF7 (continued) Table 23. Alternate function AF8 to AF15 (continued) 5 Electrical characteristics 5.1 Parameter conditions 5.1.1 Minimum and maximum values 5.1.2 Typical values 5.1.3 Typical curves 5.1.4 Loading capacitor 5.1.5 Pin input voltage Figure 25. Pin loading conditions Figure 26. Pin input voltage 5.1.6 Power supply scheme Figure 27. STM32L552xx and STM32L562xx power supply overview Figure 28. STM32L552xxxP and STM32L562xxxP power supply overview Figure 29. STM32L552xxxQ and STM32L562xxxQ power supply overview 5.1.7 Current consumption measurement Figure 30. Current consumption measurement 5.2 Absolute maximum ratings Table 24. Voltage characteristics (continued) Table 25. Current characteristics Table 26. Thermal characteristics 5.3 Operating conditions 5.3.1 General operating conditions Table 27. General operating conditions (continued) 5.3.2 SMPS step-down converter Figure 31. External components for SMPS step down converter Table 28. SMPS modes summary Table 29. SMPS characteristics 5.3.3 Operating conditions at power-up / power-down Table 30. Operating conditions at power-up / power-down 5.3.4 Embedded reset and power control block characteristics Table 31. Embedded reset and power control block characteristics (continued) 5.3.5 Embedded voltage reference Table 32. Embedded internal voltage reference Figure 32. VREFINT versus temperature 5.3.6 Supply current characteristics Table 33. Current consumption in Run and Low-power run modes, code with data processing running from Flash in single Bank, ICACHE ON in 2-way Table 34. Current consumption in Run and Low-power run modes, code with data processing running from Flash in single Bank, ICACHE ON in 1-way Table 35. Current consumption in Run and Low-power run modes, code with data processing running from Flash in single Bank, ICACHE disabled Table 36. Current consumption in Run mode, code with data processing running from Flash in single bank, ICACHE ON in 2-way and power supplied by internal SMPS step down converter Table 37. Current consumption in Run mode, code with data processing running from Flash in single bank, ICACHE ON in 1-way and power supplied by internal SMPS step down converter Table 38. Current consumption in Run mode, code with data processing running from Flash in single bank, ICACHE disabled and power supplied by internal SMPS step down converter Table 39. Current consumption in Run and Low-power run modes, code with data processing running from Flash in dual bank, ICACHE ON in 2-way Table 40. Current consumption in Run and Low-power run modes, code with data processing running from Flash in dual bank, ICACHE ON in 1-way Table 41. Current consumption in Run and Low-power run modes, code with data processing running from Flash in dual bank, ICACHE disabled Table 42. Current consumption in Run mode, code with data processing running from Flash in dual bank, ICACHE ON in 2-way and power supplied by internal SMPS step down converter Table 43. Current consumption in Run mode, code with data processing running from Flash in dual bank, ICACHE ON in 1-way and power supplied by internal SMPS step down converter Table 44. Current consumption in Run mode, code with data processing running from Flash in dual bank, ICACHE disabled and power supplied by internal SMPS step down converter Table 45. Current consumption in Run and Low-power run modes, code with data processing running from SRAM1 Table 46. Current consumption in Run mode, code with data processing running from SRAM1 and power supplied by internal SMPS step down converter Table 47. Current consumption in Run and Low-power run modes, code with data processing running from SRAM2 Table 48. Current consumption in Run mode, code with data processing running from SRAM2 and power supplied by internal SMPS step down converter Table 49. Typical current consumption in Run and Low-power run modes, with different codes running from Flash, ICACHE ON (2-way) Table 50. Typical current consumption in Run mode with SMPS, with different codes running from Flash, ICACHE ON (2-way) Table 51. Typical current consumption in Run and Low-power run modes, with different codes running from Flash, ICACHE ON (1-way) Table 52. Typical current consumption in Run mode with SMPS, with different codes running from Flash, ICACHE ON (1-way) Table 53. Typical current consumption in Run and Low-power run modes, with different codes running from Flash, ICACHE disabled Table 54. Typical current consumption in Run mode with internal SMPS, with different codes running from Flash, ICACHE disabled Table 55. Typical current consumption in Run and Low-power run modes, with different codes running from SRAM1 Table 56. Typical current consumption in Run mode with internal SMPS, with different codes running from SRAM1 Table 57. Typical current consumption in Run and Low-power run modes, with different codes running from SRAM2 Table 58. Typical current consumption in Run mode with internal SMPS, with different codes running from SRAM2 Table 59. Current consumption in Sleep and Low-power sleep mode, Flash ON Table 60. Current consumption in Low-power sleep mode, Flash in power-down Table 61. Current consumption in Sleep mode, Flash ON and power supplied by internal SMPS step down converter Table 62. Current consumption in Run mode, code with data processing running from Flash in single bank, ICACHE ON in 2-way and power supplied by external SMPS Table 63. Current consumption in Run mode, code with data processing running from Flash in single bank, ICACHE ON in 1-way and power supplied by external SMPS Table 64. Current consumption in Run mode, code with data processing running from Flash in single bank, ICACHE disabled and power supplied by external SMPS Table 65. Current consumption in Run mode, code with data processing running from Flash in dual bank, ICACHE on in 2-way and power supplied by external SMPS Table 66. Current consumption in Run mode, code with data processing running from Flash in dual bank, ICACHE on in 1-way and power supplied by external SMPS Table 67. Current consumption in Run mode, code with data processing running from Flash in dual bank, ICACHE disabled and power supplied by external SMPS Table 68. Current consumption in Run mode, code with data processing running from SRAM1, and power supplied by external SMPS Table 69. Current consumption in Run mode, code with data processing running from SRAM2, and power supplied by external SMPS Table 70. Current consumption in Sleep mode, Flash ON and power supplied by external SMPS Table 71. Current consumption in Run mode, code with data processing running from Flash, ICACHE on (2-way) and power supplied by external SMPS Table 72. Current consumption in Run mode, code with data processing running from Flash, ICACHE on (1-way) and power supplied by external SMPS Table 73. Current consumption in Run mode, code with data processing running from Flash, ICACHE disabled and power supplied by external SMPS Table 74. Current consumption in Run mode, code with data processing running from SRAM1, and power supplied by external SMPS Table 75. Current consumption in Run mode, code with data processing running from SRAM2, and power supplied by external SMPS Table 76. Current consumption in Stop 2 mode (continued) Table 77. Current consumption in Stop 1 mode (continued) Table 78. Current consumption in Stop 0 mode Table 79. Current consumption in Standby mode (continued) Table 80. Current consumption in Shutdown mode (continued) Table 81. Current consumption in VBAT mode Table 82. Peripheral current consumption (continued) 5.3.7 Wakeup time from low-power modes and voltage scaling transition times Table 83. Low-power mode wakeup timings (continued) Table 84. Regulator modes transition times Table 85. Wakeup time using USART/LPUART 5.3.8 External clock source characteristics Table 86. High-speed external user clock characteristics Figure 33. High-speed external clock source AC timing diagram Table 87. Low-speed external user clock characteristics Figure 34. Low-speed external clock source AC timing diagram Table 88. HSE oscillator characteristics Figure 35. Typical application with an 8 MHz crystal Table 89. LSE oscillator characteristics (fLSE = 32.768 kHz) Figure 36. Typical application with a 32.768 kHz crystal 5.3.9 Internal clock source characteristics Table 90. HSI16 oscillator characteristics Figure 37. HSI16 frequency versus temperature Table 91. MSI oscillator characteristics (continued) Figure 38. Typical current consumption versus MSI frequency Table 92. HSI48 oscillator characteristics Figure 39. HSI48 frequency versus temperature Table 93. LSI oscillator characteristics 5.3.10 PLL characteristics Table 94. PLL, PLLSAI1, PLLSAI2 characteristics 5.3.11 Flash memory characteristics Table 95. Flash memory characteristics Table 96. Flash memory endurance and data retention 5.3.12 EMC characteristics Table 97. EMS characteristics Table 98. EMI characteristics 5.3.13 Electrical sensitivity characteristics Table 99. ESD absolute maximum ratings Table 100. Electrical sensitivities 5.3.14 I/O current injection characteristics Table 101. I/O current injection susceptibility 5.3.15 I/O port characteristics Table 102. I/O static characteristics (continued) Figure 40. I/O input characteristics Table 103. Output voltage characteristics Table 104. I/O AC characteristics (All I/Os except FT_c) (continued) Table 105. FT_c I/O AC characteristics Figure 41. I/O AC characteristics definition(1) 5.3.16 NRST pin characteristics Table 106. NRST pin characteristics Figure 42. Recommended NRST pin protection 5.3.17 Extended interrupt and event controller input (EXTI) characteristics Table 107. EXTI input characteristics 5.3.18 Analog switches booster Table 108. Analog switches booster characteristics 5.3.19 Analog-to-digital converter characteristics Table 109. ADC characteristics Table 110. Maximum ADC RAIN Table 111. ADC accuracy - limited test conditions 1 (continued) Table 112. ADC accuracy - limited test conditions 2 (continued) Table 113. ADC accuracy - limited test conditions 3 (continued) Table 114. ADC accuracy - limited test conditions 4 (continued) Figure 43. ADC accuracy characteristics Figure 44. Typical connection diagram using the ADC 5.3.20 Digital-to-Analog converter characteristics Table 115. DAC characteristics (continued) Figure 45. 12-bit buffered / non-buffered DAC Table 116. DAC accuracy ranges 0/1 (continued) 5.3.21 Voltage reference buffer characteristics Table 117. VREFBUF characteristics (continued) Figure 46. VREFBUF in case VRS = 0 Figure 47. VREFBUF in case VRS = 1 5.3.22 Comparator characteristics Table 118. COMP characteristics (continued) 5.3.23 Operational amplifiers characteristics Table 119. OPAMP characteristics (continued) 5.3.24 Temperature sensor characteristics Table 120. TS characteristics 5.3.25 VBAT monitoring characteristics Table 121. VBAT monitoring characteristics Table 122. VBAT charging characteristics 5.3.26 Temperature and VDD thresholds monitoring Table 123. Temp and VDD monitoring characteristics 5.3.27 DFSDM characteristics Table 124. DFSDM measured timing 1.71 to 3.6 V 5.3.28 Timer characteristics Table 125. TIMx characteristics Table 126. IWDG min/max timeout period at 32 kHz (LSI) Table 127. WWDG min/max timeout value at 110 MHz (PCLK) 5.3.29 Communication interfaces characteristics Table 128. I2C analog filter characteristics Table 129. SPI characteristics (continued) Figure 48. SPI timing diagram - slave mode and CPHA = 0 Figure 49. SPI timing diagram - slave mode and CPHA = 1 Figure 50. SPI timing diagram - master mode Table 130. SAI characteristics (continued) Figure 51. SAI master timing waveforms Figure 52. SAI slave timing waveforms Table 131. USART characteristics (continued) Figure 53. USART master mode timing diagram Figure 54. USART slave mode timing diagram 5.3.30 FSMC characteristics Figure 55. Asynchronous non-multiplexed SRAM/PSRAM/NOR read waveforms Table 132. Asynchronous non-multiplexed SRAM/PSRAM/NOR read timings Table 133. Asynchronous non-multiplexed SRAM/PSRAM/NOR read-NWAIT timings Figure 56. Asynchronous non-multiplexed SRAM/PSRAM/NOR write waveforms Table 134. Asynchronous non-multiplexed SRAM/PSRAM/NOR write timings Table 135. Asynchronous non-multiplexed SRAM/PSRAM/NOR write-NWAIT timings Figure 57. Asynchronous multiplexed PSRAM/NOR read waveforms Table 136. Asynchronous multiplexed PSRAM/NOR read timings Table 137. Asynchronous multiplexed PSRAM/NOR read-NWAIT timings Figure 58. Asynchronous multiplexed PSRAM/NOR write waveforms Table 138. Asynchronous multiplexed PSRAM/NOR write timings Table 139. Asynchronous multiplexed PSRAM/NOR write-NWAIT timings Figure 59. Synchronous multiplexed NOR/PSRAM read timings Table 140. Synchronous multiplexed NOR/PSRAM read timings Figure 60. Synchronous multiplexed PSRAM write timings Table 141. Synchronous multiplexed PSRAM write timings Figure 61. Synchronous non-multiplexed NOR/PSRAM read timings Table 142. Synchronous non-multiplexed NOR/PSRAM read timings Figure 62. Synchronous non-multiplexed PSRAM write timings Table 143. Synchronous non-multiplexed PSRAM write timings Figure 63. NAND controller waveforms for read access Figure 64. NAND controller waveforms for write access Figure 65. NAND controller waveforms for common memory read access Figure 66. NAND controller waveforms for common memory write access Table 144. Switching characteristics for NAND Flash read cycles Table 145. Switching characteristics for NAND Flash write cycles 5.3.31 OCTOSPI characteristics Table 146. OCTOSPI characteristics in SDR mode Table 147. OCTOSPI characteristics in DTR mode (no DQS) Table 148. OCTOSPI characteristics in DTR mode (with DQS)/Octal and HyperBus (continued) Figure 67. OCTOSPI timing diagram - SDR mode Figure 68. OCTOSPI timing diagram - DDR mode Figure 69. OCTOSPI HyperBus clock Figure 70. OCTOSPI HyperBus read Figure 71. OCTOSPI HyperBus read with double latency Figure 72. OCTOSPI HyperBus write Table 149. Dynamics characteristics: delay block characteristics 5.3.32 SD/SDIO/MMC card host interfaces (SDMMC) Table 150. Dynamics characteristics: SD / eMMC characteristics, VDD=2.7V to 3.6 V (continued) Table 151. Dynamics characteristics: eMMC characteristics VDD=1.71 V to 1.9 V Figure 73. SDIO high-speed mode Figure 74. SD default mode Figure 75. DDR mode 5.3.33 UCPD characteristics Table 152. UCPD characteristics 6 Package information 6.1 LQFP48 package information Figure 76. LQFP48 outline Table 153. LQFP48 mechanical data (continued) Figure 77. LQFP48 recommended footprint Figure 78. Example of LQFP48 package marking (package top view) 6.2 UFQFPN48 package information Figure 79. UFQFPN48 outline Table 154. UFQFPN48 mechanical data (continued) Figure 80. UFQFPN48 recommended footprint Figure 81. Example of UFQFPN48 package marking (package top view) 6.3 LQFP64 package information Figure 82. LQFP64 outline Table 155. LQFP64 mechanical data (continued) Figure 83. LQFP64 recommended footprint Figure 84. Example of LQFP64 package marking (package top view) 6.4 WLCSP81 package information Figure 85. WLCSP81 outline Table 156. WLCSP81 mechanical data (continued) Figure 86. WLCSP 81 recommended footprint Table 157. WLCSP81 recommended PCB design rules Figure 87. Example of WLCSP81 package marking (package top view) 6.5 LQFP100 package information Figure 88. LQFP100 outline Table 158. LQPF100 mechanical data (continued) Figure 89. LQFP100 recommended footprint Figure 90. Example of LQFP100 package marking (package top view) 6.6 UFBGA132 package information Figure 91. UFBGA132 outline Table 159. UFBGA132 mechanical data (continued) Figure 92. UFBGA132 recommended footprint Table 160. UFBGA132 recommended PCB design rules (0.5 mm pitch BGA) Figure 93. Example of UFBGA132 package marking (package top view) 6.7 LQFP144 package information Figure 94. LQFP144 outline Table 161. LQFP144 mechanical data Figure 95. LQFP144 recommended footprint Figure 96. Example of LQFP144 package marking (package top view) 6.8 Thermal characteristics Table 162. Package thermal characteristics (continued) 6.8.1 Reference document 6.8.2 Selecting the product temperature range 7 Ordering information Table 163. STM32L552xx ordering information scheme 8 Revision history Table 164. Document revision history