Datasheet MAX98396 (Maxim) - 2

MAX98396 20V Digital Input Class-DG Amplifier with I/V Sense and Brownout Prevention
Simplified Block Diagram
MAX98396 DYNAMIC BROWNOUT THERMAL HEADROOM PREVENTION PROTECTION/ TRACKING ENGINE FOLDBACK DAC CLASS-DG AMP CONTROL PCM AND AUDIO BUS INTERFACES CURRENT SENSE ADC I2C I2C CONTROL VOLTAGE BUS INTERFACE SENSE ADC www.maximintegrated.com Maxim Integrated | 2 Document Outline General Description Applications Benefits and Features Simplified Block Diagram Absolute Maximum Ratings Package Information 35 WLP Electrical Characteristics Electrical Characteristics (continued) Typical Operating Characteristics Typical Operating Characteristics (continued) Pin Configuration 35 WLP Pin Description Pin Description (continued) Functional Diagrams Detailed Block Diagram Detailed Description Device State Control Hardware Shutdown State Software Shutdown State Active State Device Sequencing PCM Interface PCM Clock Configuration PCM Data Format Configuration I2S/Left-Justified Mode TDM Modes PCM Data Path Configuration PCM Data Input PCM Data Output Data Output Channel-Interleaved I/V Sense Data Data Output Status Bits PCM Interface Timing Interrupts Interrupt Bit Field Composition Interrupt Output Configuration Interrupt Sources Speaker Path Speaker Path Block Diagram Speaker Playback Path Speaker Path Noise Gate Speaker Path Dither Speaker Path Data Inversion Speaker Path DC Blocking Filter Speaker Path Digital Volume Control Speaker Path Digital Gain Control Speaker Path DSP Data Feedback Path Speaker Safe Mode Speaker Audio Processing Bypass Path Bypass Path Data Inversion Bypass Path Dither Bypass Path DC Blocking Filter Speaker Maximum Peak Output Voltage Scaling Dynamic-Headroom Tracking (DHT) DHT Supply Tracking and Headroom DHT Mode 1 – Signal Distortion Limiter DHT Mode 2 – Signal Level Limiter DHT Mode 3: Dynamic Range Compressor DHT Mode 4: Dynamic Range Compressor with Signal Level Limiter DHT Attenuation DHT Attenuation Reporting DHT Ballistics Speaker Amplifier Speaker Amplifier Operating Modes Class-DG Mode Enabled Delay for DG Mode Class-DG Mode Disabled NOVBAT Mode IDLE Mode Speaker Amplifier Ultra-Low EMI Filterless Operation Speaker Amplifier Overcurrent Protection Speaker Current and Voltage Sense ADC Path Brownout-Prevention Engine BPE State Controller and Level Thresholds BPE Level Configuration Options BPE Gain Attenuation Function BPE Limiter Function Brownout Interrupts Measurement ADC Measurement ADC Thermal Channel Measurement ADC PVDD Channel Measurement ADC VBAT Channel Clock and Data Monitors Input Data Monitor Clock Monitor Clock Activity and Frequency Detection Clock Frame Error Detection Speaker Monitor Thermal Protection Thermal Warning and Thermal Shutdown Configuration Thermal Shutdown Recovery Configuration Thermal Foldback Tone Generator Pink Noise Generator Interchip Communication ICC Operation and Data Format Multiamplifier Grouping I2C Serial Interface Slave Address Bit Transfer START and STOP Conditions Early STOP Conditions Acknowledge Write Data Format Read Data Format I2C Register Map Control Bit Field Types and Write Access Restrictions Register Map Register Map Register Details Software Reset (0x2000) Interrupt Raw 1 (0x2001) Interrupt Raw 2 (0x2002) Interrupt Raw 3 (0x2003) Interrupt Raw 4 (0x2004) Interrupt State 1 (0x2006) Interrupt State 2 (0x2007) Interrupt State 3 (0x2008) Interrupt State 4 (0x2009) Interrupt Flag 1 (0x200B) Interrupt Flag 2 (0x200C) Interrupt Flag 3 (0x200D) Interrupt Flag 4 (0x200E) Interrupt Enable 1 (0x2010) Interrupt Enable 2 (0x2011) Interrupt Enable 3 (0x2012) Interrupt Enable 4 (0x2013) Interrupt Flag Clear 1 (0x2015) Interrupt Flag Clear 2 (0x2016) Interrupt Flag Clear 3 (0x2017) Interrupt Flag Clear 4 (0x2018) IRQ Control (0x201F) Thermal Warning Threshhold (0x2020) Warning Threshold 2 (0x2021) Thermal Shutdown Threshold (0x2022) Thermal Hysteresis (0x2023) Thermal Foldback Settings (0x2024) Thermal Foldback Enable (0x2027) Noise Gate/Idle Mode Control (0x2030) Noise Gate/Idle Mode Enables (0x2033) Clock Monitor Control (0x2038) Data Monitor Control (0x2039) Speaker Monitor Threshold (0x203A) Speaker Monitor Duration (0x203B) Enable Controls (0x203F) Pin Config (0x2040) PCM Mode Config (0x2041) PCM Clock Setup (0x2042) PCM Sample Rate Setup 1 (0x2043) PCM TX Control 1 (0x2044) PCM TX Control 2 (0x2045) PCM TX Control 3 (0x2046) PCM TX Control 4 (0x2047) PCM TX Control 5 (0x2048) PCM TX Control 6 (0x2049) PCM TX Control 7 (0x204A) PCM TX Control 8 (0x204B) PCM Tx HiZ Control 1 (0x204C) PCM Tx HiZ Control 2 (0x204D) PCM Tx HiZ Control 3 (0x204E) PCM Tx HiZ Control 4 (0x204F) PCM Tx HiZ Control 5 (0x2050) PCM Tx HiZ Control6 (0x2051) PCM Tx HiZ Control 7 (0x2052) PCM Tx HiZ Control 8 (0x2053) PCM RX Source 1 (0x2055) PCM RX Source 2 (0x2056) PCM Bypass Source (0x2058) PCM TX Source Enables (0x205D) PCM Rx Enables (0x205E) PCM Tx Enables (0x205F) ICC Rx Enables A (0x2070) ICC Rx Enables B (0x2071) ICC Tx Control (0x2072) ICC Enables (0x207F) Tone Generator and DC Config (0x2083) Tone Generator DC Level 1 (0x2084) Tone Generator DC Level 2 (0x2085) Tone Generator DC Level 3 (0x2086) Tone Generator Enable (0x208F) AMP volume control (0x2090) AMP Path Gain (0x2091) AMP DSP Config (0x2092) SSM Configuration (0x2093) SPK Class DG Threshold (0x2094) SPK Class DG Headroom (0x2095) SPK Class DG Hold Time (0x2096) SPK Class DG Delay (0x2097) SPK Class DG Mode (0x2098) SPK Class DG VBAT Level (0x2099) SPK Edge Control (0x209A) SPK Path Wideband Only Enable (0x209B) SPK Edge Control 1 (0x209C) SPK Edge Control 2 (0x209D) Amp Clip Gain (0x209E) Bypass Path Config (0x209F) Amplifier Supply Control (0x20A0) AMP enables (0x20AF) Meas ADC Sample Rate (0x20B0) Meas ADC PVDD Config (0x20B1) Meas ADC VBAT Config (0x20B2) Meas ADC Thermal Config (0x20B3) Meas ADC Readback Control 1 (0x20B4) Meas ADC Readback Control 2 (0x20B5) Meas ADC PVDD Readback MSB (0x20B6) Meas ADC PVDD Readback LSB (0x20B7) Meas ADC VBAT Readback MSB (0x20B8) Meas ADC VBAT Readback LSB (0x20B9) Meas ADC Temp Readback MSB (0x20BA) Meas ADC Temp Readback LSB (0x20BB) Meas ADC Lowest PVDD Readback MSB (0x20BC) Meas ADC Lowest PVDD Readback LSB (0x20BD) Meas ADC Lowest VBAT Readback MSB (0x20BE) Meas ADC Lowest VBAT Readback LSB (0x20BF) Meas ADC Config (0x20C7) DHT Configuration 1 (0x20D0) Limiter Configuration 1 (0x20D1) Limiter Configuration 2 (0x20D2) DHT Configuration 2 (0x20D3) DHT Configuration 3 (0x20D4) DHT Configuration 4 (0x20D5) DHT Supply Hysteresis Configuration (0x20D6) DHT Enable (0x20DF) I_V Sense Path Config (0x20E0) I_V Sense Path Enables (0x20E4) BPE State (0x20E5) BPE L3 Threshold MSB (0x20E6) BPE L3 Threshold LSB (0x20E7) BPE L2 Threshold MSB (0x20E8) BPE L2 Threshold LSB (0x20E9) BPE L1 Threshold MSB (0x20EA) BPE L1 Threshold LSB (0x20EB) BPE L0 Threshold MSB (0x20EC) BPE L0 Threshold LSB (0x20ED) BPE L3 Dwell and Hold Time (0x20EE) BPE L2 Dwell and Hold Time (0x20EF) BPE L1 Dwell and Hold Time (0x20F0) BPE L0 Hold Time (0x20F1) BPE L3 Attack and Release Step (0x20F2) BPE L2 Attack and Release Step (0x20F3) BPE L1 Attack and Release Step (0x20F4) BPE L0 Attack and Release Step (0x20F5) BPE L3 Max Gain Attn (0x20F6) BPE L2 Max Gain Attn (0x20F7) BPE L1 Max Gain Attn (0x20F8) BPE L0 Max Gain Attn (0x20F9) BPE L3 Gain Attack and Rls Rates (0x20FA) BPE L2 Gain Attack and Rls Rates (0x20FB) BPE L1 Gain Attack and Rls Rates (0x20FC) BPE L0 Gain Attack and Rls Rates (0x20FD) BPE L3 Limiter Config (0x20FE) BPE L2 Limiter Config (0x20FF) BPE L1 Limiter Config (0x2100) BPE L0 Limiter Config (0x2101) BPE L3 Limiter Attack and Release Rates (0x2102) BPE L2 Limiter Attack and Release Rates (0x2103) BPE L1 Limiter Attack and Release Rates (0x2104) BPE L0 Limiter Attack and Release Rates (0x2105) BPE Threshold Hysteresis (0x2106) BPE Infinite Hold Clear (0x2107) BPE Supply Source (0x2108) BPE Lowest State (0x2109) BPE Lowest Gain (0x210A) BPE Lowest Limiter (0x210B) BPE Enable (0x210D) Auto-Restart Behavior (0x210E) Global Enable (0x210F) Revision ID (0x21FF) Applications Information Layout and Grounding Recommended External Components Typical Application Circuits Typical Application Circuit Ordering Information Revision History