Datasheet MAX4571, MAX4572, MAX4573, MAX4574 (Maxim) - 5

Serially Controlled, Clickless Audio/Video Switches MAX4571–MAX4574 I/O INTERFACE CHARACTERISTICS
(V+ = +2.7V to +5.25V, TA = TMIN to TMAX, unless otherwise noted. Typical values are at TA = +25°C.)
PARAMETER SYMBOL CONDITIONS MIN TYP MAX UNITS DIGITAL INPUTS (SCLK, DIN,
CS
, SCL, SDA, A0, A1)
V+ = 5V 0.8 Input Low Voltage VIL V V+ = 3V 0.6 V+ = 5V 3 Input High Voltage VIH V V+ = 3V 2 Input Hysteresis VHYST 0.2 V Input Leakage Current ILEAK Digital inputs = 0 or V+ -1 0.01 1 µA Input Capacitance CIN 5 pF
DIGITAL OUTPUTS (DOUT, SDA)
Output Low Voltage VOL ISINK = 6mA 0.4 V V+ DOUT Output High Voltage VOH ISOURCE = 0.5mA V - 0.5
2-WIRE INTERFACE TIMING
(Figure 3) SCL Clock Frequency fSCL DC 400 kHz Bus Free Time between Stop tBUF 1.3 µs and Start Condition START Condition Hold Time tHD:STA 0.6 µs STOP Condition Setup Time tSU:STO 0.6 µs Data Hold Time tHD:DAT 0 0.9 µs Data Setup Time tSU:DAT 100 ns Clock Low Period tLOW 1.3 µs Clock High Period tHIGH 0.6 µs 20 + SCL/SDA Rise Time tR (Note 11) 300 ns 0.1Cb 20 + SCL/SDA Fall Time tF (Note 11) 300 ns 0.1Cb
3-WIRE TIMING
(Figure 5) Operating Frequency fOP DC 2.1 MHz DIN to SCLK Setup tDS 100 ns DIN to SCLK Hold tDH 0 ns SCLK Fall to Output Data Valid tDO CLOAD = 50pF 20 200 ns CS to SCLK Rise Setup tCSS 100 ns CS to SCLK Rise Hold tCSH 0 ns CS High Pulse Width tCSW 200 ns SCLK Pulse Width Low tCL 200 ns SCLK Pulse Width High tCH 200 ns Rise Time (SCLK, DIN, CS) tR 2 µs Fall Time (SCLK, DIN, CS) tF 2 µs
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