Datasheet CYW43455 (Cypress) - 6

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CYW43455 1. CYW43455 Overview 1.1 Overview
The Cypress CYW43455 single-chip device provides the highest level of integration for IoT applications handheld wireless systems, with integrated IEEE 802.1 a/b/g/n/ac MAC/baseband/radio and, Bluetooth 5.0 + EDR (Enhanced Data Rate). It provides a small form-factor solution with minimal external components to drive down cost for mass volumes and allows for handheld device flexibility in size, form, and function. Comprehensive power management circuitry and software ensure the system can meet the needs of highly mobile devices that require minimal power consumption and reliable operation. Figure 2 shows the interconnect of all the major physical blocks in the CYW43455 and their associated external interfaces, which are described in greater detail in the following sections5 .
Figure 2. CYW43455 Block Diagram
SECI UART and GCI GPIOs GCI WL_HOST_WAKE
BT WLAN
UART WL_DEV_WKAE JTAG Other GPIOs BT_HOST_WAKE UART RAM TCM BT_DEV_WAKE l WLAN RAM Sharing RAM 800 KB o ROM ROM 704 KB SDIOD SDIO 3.0 UART ntr I2S USB 1.1 o e PCM rt C PCM o I2S P ARMCM3 plan ARMCR4 Other GPIOs USB I Back AX Registers WLAN AXI2ANB 3 Master Slave WLAN BT Access AHB2AXI PCIE PCIE WL_REG_ON C-301 BT_REG_ON NI DMA trix a s M RX/TX Chip Common u (OTP) PMU JTAG Master AXI2APB BLE AHB B GPIO LCU GCI Coex I/F DOT11MAC (D11) VBAT Timers APB APU 2 WD Shared LNA RF AHB BlueRF Control and Other 1×1 IEEE 802.11ac PHY (Rev. 4) Switch Pause Coex I/F Controls Modem 2.4 GHz/5 GHz TINY Radio XTAL BT RF CLB 32 kHz BT PA External 5 GHz PA Driver LPO Shared 2.4 LNA LNA LNA 5 GHz 2.4 GHz PA PA L L
WLAN:
5 GHz: iPA, iLNA, eLG, eTR 2 GHz: iPA, iLNA, eLG, iTR
BT: 
Shared LNA, iTR eTR Diplexer 3. The PCIe interface is not brought up on CYW43455 and Cypress's firmware and drivers do not support this interface. Document Number: 002-15051 Rev. *O Page 5 of 121 Document Outline 1. CYW43455 Overview 1.1 Overview 1.2 Standards Compliance 2. Power Supplies and Power Management 2.1 Power Supply Topology 2.2 CYW43455 PMU Features 2.3 WLAN Power Management 2.4 PMU Sequencing Each resource is in one of four states: 2.5 Power-Off Shutdown 2.6 Power-Up/Power-Down/Reset Circuits 3. Frequency References 3.1 Crystal Interface and Clock Generation 3.2 External Frequency Reference 3.3 Frequency Selection 3.4 External 32.768 kHz Low-Power Oscillator 4. Bluetooth Subsystem Overview 4.1 Features 4.2 Bluetooth Radio 4.2.1 Transmit 4.2.2 Digital Modulator 4.2.3 Digital Demodulator and Bit Synchronizer 4.2.4 Power Amplifier 4.2.5 Receiver 4.2.6 Digital Demodulator and Bit Synchronizer 4.2.7 Receiver Signal Strength Indicator 4.2.8 Local Oscillator Generation 4.2.9 Calibration 5. Bluetooth Baseband Core 5.1 Bluetooth 4.0 Features 5.2 Bluetooth 4.2 Features 5.3 Bluetooth Low Energy 5.4 Bluetooth 5.0 5.5 Link Control Layer 5.6 Test Mode Support 5.7 Bluetooth Power Management Unit 5.7.1 RF Power Management 5.7.2 Host Controller Power Management 5.7.3 BBC Power Management 5.8 Adaptive Frequency Hopping 5.9 Advanced Bluetooth/WLAN Coexistence 5.10 Fast Connection (Interlaced Page and Inquiry Scans) 6. Microprocessor and Memory Unit for Bluetooth 6.1 RAM, ROM, and Patch Memory 6.2 Reset 7. Bluetooth Peripheral Transport Unit 7.1 SPI Interface 7.2 SPI/UART Transport Detection 7.3 PCM Interface 7.3.1 Slot Mapping 7.3.2 Frame Synchronization 7.3.3 Data Formatting 7.3.4 Wideband Speech Support 7.3.5 Multiplexed Bluetooth Over PCM 7.3.6 Burst PCM Mode 7.3.7 PCM Interface Timing 7.4 UART Interface 7.5 I2S Interface 7.5.1 I2S Timing 8. WLAN Global Functions 8.1 WLAN CPU and Memory Subsystem 8.2 One-Time Programmable Memory 8.3 GPIO Interface 8.4 External Coexistence Interface 8.5 UART Interface 8.6 JTAG/SWD Interface 9. WLAN Host Interfaces 9.1 SDIO v3.0 9.2 SDIO Pins 9.3 PCI Express Interface 9.4 Transaction Layer Interface 9.4.1 Data Link Layer 9.4.2 Physical Layer 9.4.3 Logical Subblock 9.4.4 Scrambler/Descrambler 9.4.5 8B/10B Encoder/Decoder 9.4.6 Elastic FIFO 9.4.7 Electrical Subblock 9.4.8 Configuration Space 10. Wireless LAN MAC and PHY 10.1 IEEE 802.11ac MAC 10.1.1 PSM 10.1.2 WEP 10.1.3 TXE 10.1.4 RXE 10.1.5 IFS 10.1.6 TSF 10.1.7 NAV 10.1.8 MAC-PHY Interface 10.2 IEEE 802.11ac PHY 11. WLAN Radio Subsystem 11.1 Receiver Path 11.2 Transmit Path 11.3 Calibration 12. Ball Map and Pin Descriptions 12.1 Ball Map 12.2 Pin List by Pin Number 12.3 Pin List by Pin Name 12.4 Pin Descriptions 12.5 WLAN GPIO Signals and Strapping Options 12.5.1 Multiplexed Bluetooth GPIO Signals 12.6 I/O States 13. DC Characteristics 13.1 Absolute Maximum Ratings 13.2 Environmental Ratings 13.3 Electrostatic Discharge Specifications 13.4 Recommended Operating Conditions and DC Characteristics 14. Bluetooth RF Specifications 15. WLAN RF Specifications 15.1 Introduction 15.2 2.4 GHz Band General RF Specifications 15.3 WLAN 2.4 GHz Receiver Performance Specifications 15.4 WLAN 2.4 GHz Transmitter Performance Specifications 15.5 WLAN 5 GHz Receiver Performance Specifications 15.6 WLAN 5 GHz Transmitter Performance Specifications 15.7 General Spurious Emissions Specifications 15.7.1 Transmitter Spurious Emissions Specifications 15.7.2 Receiver Spurious Emissions Specifications 16. Internal Regulator Electrical Specifications 16.1 Core Buck Switching Regulator 16.2 3.3V LDO (LDO3P3) 16.3 2.5V LDO (BTLDO2P5) 16.4 CLDO 16.5 LNLDO 16.6 PCIe LDO 17. System Power Consumption 17.1 WLAN Current Consumption 17.1.1 2.4 GHz Mode 17.1.2 5 GHz Mode 17.2 Bluetooth Current Consumption 18. Interface Timing and AC Characteristics 18.1 SDIO Timing 18.1.1 SDIO Default Mode Timing 18.2 SDIO High-Speed Mode Timing 18.2.1 SDIO Bus Timing Specifications in SDR Modes 18.2.2 SDIO Bus Timing Specifications in DDR50 Mode 18.3 PCI Express Interface Parameters 18.4 JTAG Timing 18.5 SWD Timing 19. Power-Up Sequence and Timing 19.1 Sequencing of Reset and Regulator Control Signals 19.1.1 Description of Control Signals 19.1.2 Control Signal Timing Diagrams 20. Package Information 20.1 Package Thermal Characteristics 20.2 Junction Temperature Estimation and PSIJT Versus THETAJC 20.3 Environmental Characteristics 21. Mechanical Information 22. Ordering Information 23. Additional Information 23.1 Acronyms and Abbreviations 23.2 References 23.3 IoT Resources Document History Page Sales, Solutions, and Legal Information Worldwide Sales and Design Support Products PSoC® Solutions Cypress Developer Community Technical Support