Datasheet AD8555 (Analog Devices) - 5

Data Sheet AD8555
At VDD = 2.7 V, VSS = 0.0 V, VCM = 1.35 V, VO = 1.35 V, −40°C ≤ TA ≤ +125°C, unless otherwise specified.
Table 2. Parameter Symbol Conditions Min Typ Max Unit
INPUT STAGE Input Offset Voltage VOS 2 10 µV Input Offset Voltage Drift TCVOS 25 60 nV/°C Input Bias Current IB TA = 25°C 12 16 nA Input Offset Current IOS TA = 25°C 0.2 1 nA 1.5 nA Input Voltage Range 0.5 1.6 V Common-Mode Rejection Ratio CMRR VCM = 0.9 V to 1.3 V, AV = 70 80 92 dB VCM = 0.9 V to 1.3 V, AV = 1,280 96 112 dB Linearity VO = 0.2 V to 3.4 V 20 ppm VO = 0.2 V to 4.8 V 1000 ppm Differential Gain Accuracy Second Stage Gain = 17.5 to 100 0.35 % Second Stage Gain = 140 to 200 0.5 % Differential Gain Temperature Coefficient Second Stage Gain = 17.5 to 100 15 ppm/°C Second Stage Gain = 140 to 200 40 ppm/°C RF 14 18 22 kΩ RF Temperature Coefficient 700 ppm/°C DAC Accuracy AV = 70, Offset Codes = 8 to 248 0.7 % Ratiometricity AV = 70, Offset Codes = 8 to 248 50 ppm Output Offset AV = 70, Offset Codes = 8 to 248 5 35 mV Temperature Coefficient 3.3 ppm FS/°C VCLAMP Input Bias Current TA = 25°C, VCLAMP = 2.7 V 200 nA 500 nA Input Voltage Range 1.25 2.64 V OUTPUT BUFFER STAGE Buffer Offset 7 15 mV Short-Circuit Current ISC 4.5 9.5 mA Output Voltage, Low VOL RL = 10 kΩ to 5 V 30 mV Output Voltage, High VOH RL = 10 kΩ to 0 V 2.64 V POWER SUPPLY Supply Current ISY VO = 1.35 V, VPOS = VNEG = 1.35 V, 2.0 mA VDAC Code = 128 Power Supply Rejection Ratio PSRR AV = 70 109 125 dB DYNAMIC PERFORMANCE Gain Bandwidth Product GBP First Gain Stage, TA = 25°C 2 MHz Second Gain Stage, TA = 25°C 8 MHz Output Buffer Stage 1.5 MHz Output Buffer Slew Rate SR AV = 70, RL = 10 kΩ, CL = 100 pF 1.2 V/µs Settling Time ts To 0.1%, AV = 70, 4 V Output Step 8 µs NOISE PERFORMANCE Input Referred Noise TA = 25°C, f = 1 kHz 32 nV/√Hz Low Frequency Noise en p-p f = 0.1 Hz to 10 Hz 0.3 µV p-p Total Harmonic Distortion THD VIN = 16.75 mV rms, f = 1 kHz, AV = −100 dB 100 Rev. B | Page 5 of 29 Document Outline FEATURES APPLICATIONS FUNCTIONAL BLOCK DIAGRAM GENERAL DESCRIPTION TABLE OF CONTENTS REVISION HISTORY ELECTRICAL SPECIFICATIONS ABSOLUTE MAXIMUM RATINGS ESD CAUTION PIN CONFIGURATIONS AND FUNCTION DESCRIPTIONS TYPICAL PERFORMANCE CHARACTERISTICS THEORY OF OPERATION GAIN VALUES OPEN WIRE FAULT DETECTION SHORTED WIRE FAULT DETECTION FLOATING VPOS, VNEG, OR VCLAMP FAULT DETECTION DEVICE PROGRAMMING Digital Interface Initial State Simulation Mode Programming Mode Parity Error Detection Read Mode Sense Current Suggested Programming Procedure Suggested Algorithm to Determine Optimal Gain and Offset Codes FILTERING FUNCTION DRIVING CAPACITIVE LOADS RF INTERFERENCE SINGLE-SUPPLY DATA ACQUISITION SYSTEM USING THE AD8555 WITH CAPACITIVE SENSORS OUTLINE DIMENSIONS ORDERING GUIDE