Datasheet AD8555 (Analog Devices) - 8

AD8555 Data Sheet PIN CONFIGURATIONS AND FUNCTION DESCRIPTIONS VDD 1 8 VSS FILT/DIGOUT 2 AD8555 7 VOUT TOP VIEW DIGIN 3 6 VCLAMP (Not to Scale) VNEG 4 5 VPOS
04598-0-049 Figure 2. 8-Lead SOIC (Not Drawn to Scale)
Table 5. 8-Lead SOIC Pin Function Descriptions Pin No. Mnemonic Description
1 VDD Positive Supply Voltage. 2 FILT/DIGOUT Unbuffered Amplifier Output In Series with a Resistor RF. Adding a capacitor between FILT and VDD or VSS implements a low-pass filtering function. In read mode, this pin functions as a digital output. 3 DIGIN Digital Input. 4 VNEG Negative Amplifier Input (Inverting Input). 5 VPOS Positive Amplifier Input (Noninverting Input). 6 VCLAMP Set Clamp Voltage at Output. 7 VOUT Buffered Amplifier Output. Buffered version of the signal at the FILT/DIGOUT pin. In read mode, VOUT is a buffered digital output. 8 VSS Negative Supply Voltage. Rev. B | Page 8 of 29 Document Outline FEATURES APPLICATIONS FUNCTIONAL BLOCK DIAGRAM GENERAL DESCRIPTION TABLE OF CONTENTS REVISION HISTORY ELECTRICAL SPECIFICATIONS ABSOLUTE MAXIMUM RATINGS ESD CAUTION PIN CONFIGURATIONS AND FUNCTION DESCRIPTIONS TYPICAL PERFORMANCE CHARACTERISTICS THEORY OF OPERATION GAIN VALUES OPEN WIRE FAULT DETECTION SHORTED WIRE FAULT DETECTION FLOATING VPOS, VNEG, OR VCLAMP FAULT DETECTION DEVICE PROGRAMMING Digital Interface Initial State Simulation Mode Programming Mode Parity Error Detection Read Mode Sense Current Suggested Programming Procedure Suggested Algorithm to Determine Optimal Gain and Offset Codes FILTERING FUNCTION DRIVING CAPACITIVE LOADS RF INTERFERENCE SINGLE-SUPPLY DATA ACQUISITION SYSTEM USING THE AD8555 WITH CAPACITIVE SENSORS OUTLINE DIMENSIONS ORDERING GUIDE