Datasheet ALT80800 (Allegro) - 6
| 制造商 | Allegro |
| 描述 | Automotive-Grade, Constant-Current 2.0 A PWM Dimmable Synchronous Buck LED Driver |
| 页数 / 页 | 23 / 6 — Automotive-Grade, Constant-Current 2.0 A. ALT80800. PWM Dimmable … |
| 文件格式/大小 | PDF / 2.2 Mb |
| 文件语言 | 英语 |
Automotive-Grade, Constant-Current 2.0 A. ALT80800. PWM Dimmable Synchronous Buck LED Driver
该数据表的模型线
文件文字版本
Automotive-Grade, Constant-Current 2.0 A ALT80800 PWM Dimmable Synchronous Buck LED Driver ELECTRICAL CHARACTERISTICS (continued): Valid at VIN = 12 V, VOUT = 6 V, TJ = –40°C to 125°C, typical values at TJ = 25°C, unless otherwise noted Characteristics Symbol Test Conditions Min. Typ. Max. Unit ANALOG DIMMING INPUT
Input Voltage for 100% LED Current VADIMH VCSH – VCSL = VCSREG 2.1 – – V Regulation Threshold at 50% Analog Dimming VCSREG50 VADIM = 1.0 V – 100 – mV Regulaton Threshold at 20% Analog Dimming VCSREG20 VADIM = 0.4 V 38.4 40 41.4 mV
FAULT
LED Open/Short Detect Condition ADIM Range VADIM rising 244 264 284 mV LED Short Fault Output Voltage Low Threshold VOUT falling 1.3 1.5 1.7 V LED Open-Fault Enable Reference VREF1 2.352 2.4 2.448 V LED Open Fault Current Threshold V VCSREG falling (PWM duty = max), VADIM = (20 mV) (50 mV) (80 mV) CS_OPEN VCC, VFDSET = VCC 10% 25% 40% – LED Open Fault Current Hysteresis [1] V VCSREG rising (PWM duty = max), VADIM = (6 mV) (12 mV) (18 mV) CS_OPEN_HYS VCC, VFDSET = VCC 3% 6% 9% – Fault Deglitch Timer tFDG 35 50 65 µs Fault Mask Timer tMASK 70 100 130 µs FFn Pull-Down Voltage VFAULT(PD) Fault condition asserted, pull-up current = 1 mA – – 0.4 V FFn Pin Leakage Current IFAULT(LKG) Fault condition cleared, pull-up to 5 V – – 1 µA FFn Rising Time [1] t The transition time FFn pin takes from Low RISE to High – – 10 µs FFn Falling Time [1] t The transition time FFn pin takes from High FALL to Low – – 10 µs Cool Down Timer for Fault Retry tRETRY – 1 – ms
THERMAL SHUTDOWN
Thermal Shutdown Threshold [1] TSD 150 165 180 °C Thermal Shutdown Hysteresis TSDHYS – 25 – °C [1] Determined by design and characterization. Not production tested. [2] Guaranteed by design, HS and LS switches are interlocked, as illustrated below: SW tOFFmin tdead ≈ (tOFFMIN – tLS_ONmin) / 2 tLS_ONmin Low Side VGS tdead tdead [3] In test mode, a ramp signal is applied between CSH and CSL pins to determine the VCSH – VCSL regulation threshold voltage. In actual application, the average VCSH – VCSL voltage is regulated at VCSREG regardless of ripple voltage. [4] Negative current is defined as coming out of (sourcing) the specified device pin or node. 6 Allegro MicroSystems 955 Perimeter Road Manchester, NH 03103-3353 U.S.A. www.allegromicro.com Document Outline Features and Benefits Description Applications Package Typical Application Circuit Selection Guide Specifications Absolute Maximum Ratings Thermal Characteristics Pinout Diagrams and Terminal List Tables Functional Block Diagrams Electrical Characteristics Functional Description Application Circuit Diagrams
Input Voltage for 100% LED Current VADIMH VCSH – VCSL = VCSREG 2.1 – – V Regulation Threshold at 50% Analog Dimming VCSREG50 VADIM = 1.0 V – 100 – mV Regulaton Threshold at 20% Analog Dimming VCSREG20 VADIM = 0.4 V 38.4 40 41.4 mV
FAULT
LED Open/Short Detect Condition ADIM Range VADIM rising 244 264 284 mV LED Short Fault Output Voltage Low Threshold VOUT falling 1.3 1.5 1.7 V LED Open-Fault Enable Reference VREF1 2.352 2.4 2.448 V LED Open Fault Current Threshold V VCSREG falling (PWM duty = max), VADIM = (20 mV) (50 mV) (80 mV) CS_OPEN VCC, VFDSET = VCC 10% 25% 40% – LED Open Fault Current Hysteresis [1] V VCSREG rising (PWM duty = max), VADIM = (6 mV) (12 mV) (18 mV) CS_OPEN_HYS VCC, VFDSET = VCC 3% 6% 9% – Fault Deglitch Timer tFDG 35 50 65 µs Fault Mask Timer tMASK 70 100 130 µs FFn Pull-Down Voltage VFAULT(PD) Fault condition asserted, pull-up current = 1 mA – – 0.4 V FFn Pin Leakage Current IFAULT(LKG) Fault condition cleared, pull-up to 5 V – – 1 µA FFn Rising Time [1] t The transition time FFn pin takes from Low RISE to High – – 10 µs FFn Falling Time [1] t The transition time FFn pin takes from High FALL to Low – – 10 µs Cool Down Timer for Fault Retry tRETRY – 1 – ms
THERMAL SHUTDOWN
Thermal Shutdown Threshold [1] TSD 150 165 180 °C Thermal Shutdown Hysteresis TSDHYS – 25 – °C [1] Determined by design and characterization. Not production tested. [2] Guaranteed by design, HS and LS switches are interlocked, as illustrated below: SW tOFFmin tdead ≈ (tOFFMIN – tLS_ONmin) / 2 tLS_ONmin Low Side VGS tdead tdead [3] In test mode, a ramp signal is applied between CSH and CSL pins to determine the VCSH – VCSL regulation threshold voltage. In actual application, the average VCSH – VCSL voltage is regulated at VCSREG regardless of ripple voltage. [4] Negative current is defined as coming out of (sourcing) the specified device pin or node. 6 Allegro MicroSystems 955 Perimeter Road Manchester, NH 03103-3353 U.S.A. www.allegromicro.com Document Outline Features and Benefits Description Applications Package Typical Application Circuit Selection Guide Specifications Absolute Maximum Ratings Thermal Characteristics Pinout Diagrams and Terminal List Tables Functional Block Diagrams Electrical Characteristics Functional Description Application Circuit Diagrams