Preliminary Datasheet EPC23101 (Efficient Power Conversion) - 6
| 制造商 | Efficient Power Conversion |
| 描述 | ePower Chipset 100 V, 65 A |
| 页数 / 页 | 9 / 6 — eGaN® FET DATASHEET. Electrical Characteristics. Electrical … |
| 文件格式/大小 | PDF / 983 Kb |
| 文件语言 | 英语 |
eGaN® FET DATASHEET. Electrical Characteristics. Electrical Characteristics (continued). SYMBOL. PARAMETER. TEST CONDITIONS. MIN. TYP
该数据表的模型线
文件文字版本
eGaN® FET DATASHEET
EPC23101
Electrical Characteristics
(continued)
Electrical Characteristics (continued) SYMBOL PARAMETER TEST CONDITIONS MIN TYP MAX UNITS Dynamic Characteristics (Logic Input to Output Switching Node)
See Figure 6. Timing Diagram and Test Circuit EPC23101 + EPC2302) t_delayHS_on High-Side On Propagation Delay SW = 0 V and HS FET Turn-On 20 t_delayLS_on Low-Side On Propagation Delay SW = 48 V and LS FET Turn-On 20 t_delayHS_off High-Side Off Propagation Delay SW = 48 V and HS FET Turn-Off 20 t_delayLS_off Low-Side Off Propagation Delay SW = 0 V and LS FET Turn-Off 20 t_matchon Delay Matching LSoff to HSon LS Turn-Off to HS Turn-On 0 t_matchoff Delay Matching HSoff to LSon HS Turn-Off to LS Turn-On 0 PW_min Minimum Input Pulse-Width 50% to 50% Width 20 ns t_riseSW_HS0 SW Rise Time at High Side FET Turn-On HS Turn-On Buck Mode, 0 V to 48 V, RBOOT = 0 Ω, ILoad = 5 A 1.5 (Buck Mode, Hard Switching) t_riseSW_HS1 HS Turn-On Buck Mode, 0 V to 48 V, RBOOT = 2.2 Ω, ILoad = 5 A 3 t_fallSW_LS0 SW Fall Time at Low Side FET Turn-On LS Turn-On Boost Mode, 48 V to 0 V, RDRV = 0 Ω, ILoad = 5 A 1.5 (Boost Mode, Hard Switching) t_fallSW_LS1 LS Turn-On Boost Mode, 48 V to 0 V, RDRV= 2.2 Ω , ILoad = 5 A 3 t_riseLGOUT_0 LG Low Side Gate Drive Rise Time OUT Turn-On, RDRV = 0 Ω, CL = 4000 pF 4.5 t_riseLGOUT_1 LGOUT Turn-On, RDRV = 2.2 Ω, CL = 4000 pF 9 t_fallLGOUT_0 Low Side Gate Drive Fall Time LGOUT Turn-Off, RGATE = 0 Ω, CL = 4000 pF 3
Dynamic Characteristics Parameter Definition
VIN VDRV RDRV 100 nF 5V 1 mF 48 V RDRV VBOOT RBOOT High side 37.4 W VDD RBOOT 2.2 mH input (5 V, 50 W) HSIN SW RGATE 150 W 150 W 100 nF LGOUT EPC2302 47 mF 5 A LSIN 1 kW 5 W GND Low side EN 37.4 W input
EPC23101
(5 V, 50 W) SWa To oscil oscope 50 W (50 W) 150 W 150 W To To To 2.5 V oscil oscope oscil oscope oscil oscope 50% (50 W) (50 W) (10 MW)
HSIN Figure 5a: Test Circuit for Dynamic Characteristics LSIN
2.5 V 50% t_fal LGOUT t_riseLGOUT 5 V 90%
LGOUT
10% t_delay ~1.17 V HS_off 30 mV ~1.05 V t_riseSW t_fal SW
SWa
~0.12 V ~0 V -30 mV t_delayLS_off t_delayHS_on t_delayLS_on
Figure 5b: Logic Input to Output Switching Node Timing Diagram
EPC – POWER CONVERSION TECHNOLOGY LEADER | EPC-CO.COM | ©2021 | | 6
EPC23101
Electrical Characteristics
(continued)
Electrical Characteristics (continued) SYMBOL PARAMETER TEST CONDITIONS MIN TYP MAX UNITS Dynamic Characteristics (Logic Input to Output Switching Node)
See Figure 6. Timing Diagram and Test Circuit EPC23101 + EPC2302) t_delayHS_on High-Side On Propagation Delay SW = 0 V and HS FET Turn-On 20 t_delayLS_on Low-Side On Propagation Delay SW = 48 V and LS FET Turn-On 20 t_delayHS_off High-Side Off Propagation Delay SW = 48 V and HS FET Turn-Off 20 t_delayLS_off Low-Side Off Propagation Delay SW = 0 V and LS FET Turn-Off 20 t_matchon Delay Matching LSoff to HSon LS Turn-Off to HS Turn-On 0 t_matchoff Delay Matching HSoff to LSon HS Turn-Off to LS Turn-On 0 PW_min Minimum Input Pulse-Width 50% to 50% Width 20 ns t_riseSW_HS0 SW Rise Time at High Side FET Turn-On HS Turn-On Buck Mode, 0 V to 48 V, RBOOT = 0 Ω, ILoad = 5 A 1.5 (Buck Mode, Hard Switching) t_riseSW_HS1 HS Turn-On Buck Mode, 0 V to 48 V, RBOOT = 2.2 Ω, ILoad = 5 A 3 t_fallSW_LS0 SW Fall Time at Low Side FET Turn-On LS Turn-On Boost Mode, 48 V to 0 V, RDRV = 0 Ω, ILoad = 5 A 1.5 (Boost Mode, Hard Switching) t_fallSW_LS1 LS Turn-On Boost Mode, 48 V to 0 V, RDRV= 2.2 Ω , ILoad = 5 A 3 t_riseLGOUT_0 LG Low Side Gate Drive Rise Time OUT Turn-On, RDRV = 0 Ω, CL = 4000 pF 4.5 t_riseLGOUT_1 LGOUT Turn-On, RDRV = 2.2 Ω, CL = 4000 pF 9 t_fallLGOUT_0 Low Side Gate Drive Fall Time LGOUT Turn-Off, RGATE = 0 Ω, CL = 4000 pF 3
Dynamic Characteristics Parameter Definition
VIN VDRV RDRV 100 nF 5V 1 mF 48 V RDRV VBOOT RBOOT High side 37.4 W VDD RBOOT 2.2 mH input (5 V, 50 W) HSIN SW RGATE 150 W 150 W 100 nF LGOUT EPC2302 47 mF 5 A LSIN 1 kW 5 W GND Low side EN 37.4 W input
EPC23101
(5 V, 50 W) SWa To oscil oscope 50 W (50 W) 150 W 150 W To To To 2.5 V oscil oscope oscil oscope oscil oscope 50% (50 W) (50 W) (10 MW)
HSIN Figure 5a: Test Circuit for Dynamic Characteristics LSIN
2.5 V 50% t_fal LGOUT t_riseLGOUT 5 V 90%
LGOUT
10% t_delay ~1.17 V HS_off 30 mV ~1.05 V t_riseSW t_fal SW
SWa
~0.12 V ~0 V -30 mV t_delayLS_off t_delayHS_on t_delayLS_on
Figure 5b: Logic Input to Output Switching Node Timing Diagram
EPC – POWER CONVERSION TECHNOLOGY LEADER | EPC-CO.COM | ©2021 | | 6