Datasheet AEM00330 (E-peas) - 6

DATASHEET AEM00330
Y G[4] G[5] UP D G[2] G[1] G[0] O CK A O_RD VL_CF VL_CF T ST LOA _ _ O_CF O_CF O_CF C_L C_L T_B T_S T T T ST EN_SLEEP S S ST S S S SR SR 40 39 38 37 36 35 34 33 32 31 CS_IN 1 30 SRC_LVL_CFG[3] GND 2 29 STO_PRIO SRC 3 28 EN_HP GND 4 27 STO_CFG[3] GND 5 26 LOAD_CFG[2] GND QFN40 6 25 LOAD_CFG[1] Top view BUFSRC 7 24 LOAD_CFG[0] LIN 8 23 STO_OVCH LOUT 9 22 STO_RDY GND 10 21 STO_OVDIS 11 12 13 14 15 16 17 18 19 20 L D O A BA ST G[0] G[1] VINT GND G[2] GND LO O_CH T VL_CF VL_CF VL_CF EN_S C_L C_L C_L SR SR SR Figure 2: Pinout Diagram QFN 40-pin NAME PIN NUMBER FUNCTION Power pins CS_IN 1 Input for the external cold start circuit. SRC 3 Connection to the harvested energy source. BUFSRC 7 Connection to an external capacitor buffering the DCDC converter input. LIN 8 DCDC inductance connection. LOUT 9 DCDC inductance connection. VINT 13 Internal voltage supply. On QFN48 package, both pins must be tied together. LOAD 17 Output voltage to supply the load. Connection to the energy storage element - battery or (super-)capacitor. STO 19 Cannot be left floating. Must be connected to a minimum capacitance of 100 μF or to a rechargeable battery. On QFN48 package, both pins must be tied together. BAL 18 Connection to mid-point of a dual-cel supercapacitor (optional). Must be connected to GND if not used. Status pins ST_STO 40 Logic output. Asserted when the storage device voltage VSTO rises above the VCHRDY threshold, reset when VSTO drops below the VOVDIS threshold. High level is VSTO. ST_LOAD 36 Logic output. Asserted when the LOAD voltage VLOAD rises above the VLOAD,TYP threshold. Reset when VLOAD drops below VLOAD,MIN threshold. High level is VLOAD. ST_STO_RDY 37 Logic output. Asserted when VSTO is above VCHRDY, reset when VSTO drops below VCHRDY. High level is VLOAD. ST_STO_OVDIS 38 Logic output. Asserted when the AEM00330 state is SHUTDOWN STATE or PRIMARY BATTERY STATE, reset when in any other state. High level is VLOAD. Table 1: Power and Status Pins DS D _A _ E A M0 M 033 3 0_Rev e 1.0. 0 0 Copyr y ight h © 2022 2 e-pe p as a SA S Confidential 6 Document Outline Table of Contents List of Tables 1. Introduction 2. Absolute Maximum Ratings 3. Thermal Resistance 4. Typical Electrical Characteristics at 25 °C 5. Recommended Operation Conditions 6. Functional Block Diagram 7. Theory of Operation 7.1. DCDC Converter 7.2. Reset, Wake Up and Start States 7.2.1. Storage Element Priority Supercapacitor as a Storage Element Battery as a Storage Element 7.2.2. Load Priority 7.3. Supply State 7.4. Shutdown State 7.5. Sleep State 7.6. Source Voltage Regulation 7.7. Balancing for Dual-Cell Supercapacitor 8. System Configuration 8.1. High Power / Low Power Mode 8.2. Storage Element Configuration 8.3. Load Configuration 8.4. Custom Mode Configuration 8.5. Disable Storage Element Charging 8.6. Source Level Configuration 8.7. External Components 8.7.1. Storage element information 8.7.2. External inductor information 8.7.3. External capacitors information CSRC CINT CLOAD 9. Typical Application Circuits 9.1. Example Circuit 1 9.2. Example Circuit 2 9.3. Circuit Behaviour 9.4. DCDC Conversion Efficiency From SRC to STO in Low Power Mode 9.4. DCDC Conversion Efficiency From SRC to STO in Low Power Mode 9.5. DCDC Conversion Efficiency From SRC to STO in High Power Mode 9.6. DCDC Conversion Efficiency From STO to LOAD in Low Power Mode 9.7. DCDC Conversion Efficiency From STO to LOAD in High Power Mode 10. Schematic 11. Layout 12. Package Information 12.1. Plastic Quad Flatpack No-Lead (QFN 40-pin 5x5mm) 12.2. Board Layout 13. Revision History