Datasheet ADGS1208, ADGS1209 (Analog Devices)

SPI Interface, Low CON and QINJ, ±15 V/+12 V, 1.8 V Logic Control, 8:1/Dual 4:1 Mux Switches Data Sheet ADGS1208/ ADGS1209 FEATURES FUNCTIONAL BLOCK DIAGRAMS SPI interface with error detection ADGS1208 Includes CRC, invalid read/write address, and SCLK count S1 error detection Supports burst mode and daisy-chain mode Industry standard SPI Mode 0 and SPI Mode 3 interface D compatible Round robin mode allows switching times that are comparable with a parallel interface S8 Four general-purpose digital outputs that can be used to GPO1 control other devices CNV GPO2 SPI GPO3 INTERFACE SDO <1 pC charge injection over full signal range GPO4 1 pF off capacitance
1 0 0 4-
VSS to VDD analog signal range SCLK SDI CS RESET/VL
672 1
Fully specified at ±15 V and +12 V
Figure 1. ADGS1208 Functional Block Diagram
1.8 V logic compatibility with 2.7 V ≤ VL ≤ 3.3 V ADGS1209 24-lead LFCSP package S1A APPLICATIONS DA S4A Audio and video routing Automatic test equipment Data acquisition systems S1B Battery-powered systems DB Sample-and-hold systems S4B Communication systems GPO1 CNV GPO2 SPI GENERAL DESCRIPTION GPO3 INTERFACE SDO GPO4
The ADGS1208/ADGS1209 are analog multiplexers comprising 2 -00 4 eight single channels and four differential channels, respectively. A
SCLK SDI CS RESET/VL
72 16 serial peripheral interface (SPI) controls the switches. The SPI Figure 2. ADGS1209 Functional Block Diagram interface has robust error detection features, such as cyclic The ultralow on capacitance (CON) and exceptionally low charge redundancy check (CRC) error detection, invalid read/write injection (QINJ) of these multiplexers make them ideal solutions address detection, and SCLK count error detection. for data acquisition and sample-and-hold applications, where It is possible to daisy-chain multiple ADGS1208/ADGS1209 low glitch and fast settling are required. devices together. Daisy-chain mode enables the configuration of
PRODUCT HIGHLIGHTS
multiple devices with a minimal amount of digital lines. The 1. SPI interface removes the need for parallel conversion, ADGS1208/ADGS1209 can also operate in burst mode to logic traces, and reduces GPIO channel count. decrease the time between SPI commands. 2. Daisy-chain mode removes additional logic traces when iCMOS® construction ensures ultralow power dissipation, multiple devices are used. making the devices ideally suited for portable and battery- 3. CRC error detection, invalid read/write address detection, powered instruments. and SCLK count error detection ensure a robust digital Each switch conducts equally well in both directions when on, interface. and each switch has an input signal range that extends to the 4. CRC and error detection capabilities allow the use of the supplies. In the off condition, signal levels up to the supplies ADGS1208/ADGS1209 in safety critical systems. are blocked.
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Document Outline Features Applications General Description Functional Block Diagrams Product Highlights Revision History Specifications ±15 V Dual Supply 12 V Single Supply Continuous Current per Channel, Sx or Dx Timing Characteristics Timing Diagrams Absolute Maximum Ratings Thermal Resistance ESD Caution Pin Configurations and Function Descriptions Typical Performance Characteristics Test Circuits Terminology Theory of Operation Address Mode Error Detection Features Cyclic Redundancy Check (CRC) Error Detection SCLK Count Error Detection Invalid Read/Write Address Error Detection Clearing the Error Flags Register Burst Mode Software Reset Daisy-Chain Mode Power-On Reset Round Robin Mode General-Purpose Outputs Applications Information Digital Input Buffers Settling Time Power Supply Rails Power Supply Recommendations Register Summaries Register Details Switch Data Register Error Configuration Register Error Flags Register Burst Enable Register Round Robin Enable Register Round Robin Channel Configuration Register CNV Edge Select Register Software Reset Register Outline Dimensions Ordering Guide