Datasheet ADGS5412 (Analog Devices) - 7

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Data Sheet ADGS5412 12 V SINGLE SUPPLY
VDD = 12 V ± 10%, VSS = 0 V, VL = 2.7 V to 5.5 V, GND = 0 V, unless otherwise noted.
Table 3. Parameter +25°C −40°C to +85°C −40°C to +125°C Unit Test Conditions/Comments
ANALOG SWITCH Analog Signal Range 0 V to VDD V On-Resistance, RON 19 Ω typ VS = 0 V to 10 V, IS = −10 mA; see Figure 29 22 27 31 Ω max VDD = 10.8 V, VSS = 0 V On-Resistance Match Between Channels, 0.4 Ω typ VS = 0 V to 10 V, IS = −10 mA ∆RON 0.8 1 1.2 Ω max On-Resistance Flatness, RFLAT (ON) 4.4 Ω typ VS = 0 V to 10 V, IS = −10 mA 5.5 6.5 7.5 Ω max LEAKAGE CURRENTS VDD = 13.2 V, VSS = 0 V Source Off Leakage, IS (Off) ±0.05 nA typ VS = 1 V/10 V, VD = 10 V/1 V; see Figure 32 ±0.25 ±0.75 ±6 nA max Drain Off Leakage, ID (Off) ±0.05 nA typ VS = 1 V/10 V, VD = 10 V/1 V; see Figure 32 ±0.25 ±0.75 ±6 nA max Channel On Leakage, ID (On), IS (On) ±0.1 nA typ VS = VD = 1 V/10 V; see Figure 28 ±0.4 ±2 ±12 nA max DIGITAL OUTPUT Output Voltage Low, VOL 0.4 V max ISINK = 5 mA 0.2 V max ISINK = 1 mA High Impedance Leakage Current 0.002 µA typ VOUT = VGND or VL ±0.1 µA max High Impedance Output Capacitance 4 pF typ DIGITAL INPUTS Input Voltage High, VINH 2 V min 3.3 V < VL ≤ 5.5 V 1.35 V min 2.7 V ≤ VL ≤ 3.3 V Low, VINL 0.8 V max 3.3 V < VL ≤ 5.5 V 0.8 V max 2.7 V ≤ VL ≤ 3.3 V Input Current, IINL or IINH 0.001 µA typ VIN = VGND or VL ±0.1 µA max Digital Input Capacitance, CIN 4 pF typ DYNAMIC CHARACTERISTICS1 tON 545 ns typ RL = 300 Ω, CL = 35 pF 665 720 775 ns max VS = 8 V; see Figure 36 tOFF 200 ns typ RL = 300 Ω, CL = 35 pF 250 275 305 ns max VS = 8 V; see Figure 36 Break-Before-Make Time Delay, tD 320 ns typ RL = 300 Ω, CL = 35 pF 235 ns min VS1 = VS2 = 8 V, see Figure 35 Charge Injection, QINJ 105 pC typ VS = 6 V, RS = 0 Ω, CL = 1 nF; see Figure 37 Off Isolation −78 dB typ RL = 50 Ω, CL = 5 pF, f = 100 kHz; see Figure 31 Channel-to-Channel Crosstalk −70 dB typ RL = 50 Ω, CL = 5 pF, f = 1 MHz; see Figure 30 Total Harmonic Distortion + Noise, 0.08 % typ RL = 1 kΩ, 6 V p-p, f = 20 Hz THD + N to 20 kHz; see Figure 33 Rev. A | Page 7 of 30 Document Outline FEATURES APPLICATIONS FUNCTIONAL BLOCK DIAGRAM GENERAL DESCRIPTION PRODUCT HIGHLIGHTS TABLE OF CONTENTS REVISION HISTORY SPECIFICATIONS ±15 V DUAL SUPPLY ±20 V DUAL SUPPLY 12 V SINGLE SUPPLY 36 V SINGLE SUPPLY CONTINUOUS CURRENT PER CHANNEL, SX OR DX TIMING CHARACTERISTICS ABSOLUTE MAXIMUM RATINGS ESD CAUTION PIN CONFIGURATIONS AND FUNCTION DESCRIPTIONS TYPICAL PERFORMANCE CHARACTERISTICS TEST CIRCUITS TERMINOLOGY THEORY OF OPERATION ADDRESS MODE ERROR DETECTION FEATURES Cyclic Redundancy Check (CRC) Error Detection SCLK Count Error Detection Invalid Read/Write Address Error CLEARING THE ERROR FLAGS REGISTER BURST MODE SOFTWARE RESET DAISY-CHAIN MODE POWER-ON RESET BREAK-BEFORE-MAKE SWITCHING TRENCH ISOLATION DIGITAL INPUT BUFFERS APPLICATIONS INFORMATION POWER SUPPLY RAILS POWER SUPPLY RECOMMENDATIONS REGISTER SUMMARY REGISTER DETAILS SWITCH DATA REGISTER Address: 0x01, Reset: 0x00, Name: SW_DATA ERROR CONFIGURATION REGISTER Address: 0x02, Reset: 0x06, Name: ERR_CONFIG ERROR FLAGS REGISTER Address: 0x03, Reset: 0x00, Name: ERR_FLAGS BURST ENABLE REGISTER Address: 0x05, Reset: 0x00, Name: BURST_EN SOFTWARE RESET REGISTER Address: 0x0B, Reset: 0x00, Name: SOFT_RESETB OUTLINE DIMENSIONS ORDERING GUIDE