Datasheet ADG798 (Analog Devices) - 3
| 制造商 | Analog Devices |
| 描述 | High Temperature, Low Voltage 8-Channel Multiplexer |
| 页数 / 页 | 22 / 3 — Data Sheet. ADG798. SPECIFICATIONS. Table 1. TSSOP. FLATPACK. Parameter. … |
| 修订版 | A |
| 文件格式/大小 | PDF / 433 Kb |
| 文件语言 | 英语 |
Data Sheet. ADG798. SPECIFICATIONS. Table 1. TSSOP. FLATPACK. Parameter. Symbol Test Conditions/Comments1. Min. Typ2. Max. Typ. Unit
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Data Sheet ADG798 SPECIFICATIONS
VDD = 5 V ± 10%, VSS = 0 V, GND = 0 V, unless otherwise noted. TSSOP temperature range = −55°C ≤ TA ≤ +175°C and FLATPACK temperature range = −55°C ≤ TA ≤ +210°C, unless otherwise noted.
Table 1. TSSOP FLATPACK Parameter Symbol Test Conditions/Comments1 Min Typ2 Max Min Typ
2
Max Unit
ANALOG SWITCH Analog Signal Range 0 VDD 0 VDD V On Resistance RON VS = 0 V to VDD, IDS = 10 mA; see 4.5 9 5 10 Ω Figure 24 Matching Between ΔRON VS = 0 V to VDD, IDS = 10 mA 0.6 1.2 1.25 1.5 Ω Channels Flatness RFLAT (ON) VS = 0 V to VDD, IDS = 10 mA 1.5 0.75 2 Ω LEAKAGE CURRENTS VDD = 5.5 V Source Off Leakage IS (Off) VD = 4.5 V/1 V, VS = 1 V/4.5 V; see −50 ±0.01 +50 −180 ±0.01 +180 nA Figure 25 Drain Off Leakage ID (Off) VD = 4.5 V/1 V, VS = 1 V/4.5 V; see −650 ±0.01 +650 −2600 ±0.01 +2600 nA Figure 26 Channel On Leakage ID (On), VD = VS = 1 V or 4.5 V; see Figure 27 −650 ±0.01 +650 −2600 ±0.01 +2600 nA IS (On) DIGITAL INPUTS Input Voltage High VINH 2.4 2.4 V Low VINL 0.8 0.8 V Input Current IINL or VIN = VINL or VINH −800 +0.005 +800 −800 +0.005 +800 nA IINH Digital Input Capacitance CIN 2 2 pF DYNAMIC CHARACTERISTICS3 Transition Time tTRANSITION RL = 150 Ω, CL = 15 pF; see 12 21 12 23 ns Figure 28 VS1 = 3 V/0 V, VS8 = 0 V/3 V Break-Before-Make Time tOPEN RL = 150 Ω, CL = 15 pF, VS = 3 V; 1 8 1 8 ns Delay see Figure 29 TA = maximum temperature 9 9 ns On Time tON (EN) RL = 150 Ω, CL = 15 pF 11 17 11 20 ns VS = 3 V; see Figure 30 Off Time tOFF (EN) RL = 150 Ω, CL = 15 pF 5.5 11 5.5 12 ns VS = 3 V; see Figure 30 Charge Injection QINJ VS = 2.5 V, RS = 0 Ω, CL = 1 nF; see ±3 ±3 pC Figure 31 Off Isolation RL = 50 Ω, CL = 5 pF, f = 10 MHz −60 −60 dB RL = 50 Ω, CL = 5 pF, f = 1 MHz; see −80 −80 dB Figure 32 Channel to Channel RL = 50 Ω, CL = 5 pF, f = 10 MHz −60 −60 dB Crosstalk RL = 50 Ω, CL = 5 pF, f = 1 MHz; see −80 −80 dB Figure 33 −3 dB Bandwidth RL = 50 Ω, CL = 5 pF; see Figure 34 55 55 MHz Source Capacitance, Off CS (Off) f = 1 MHz 13 13 pF Rev. A | Page 3 of 22 Document Outline FEATURES APPLICATIONS FUNCTIONAL BLOCK DIAGRAM GENERAL DESCRIPTION PRODUCT HIGHLIGHTS TABLE OF CONTENTS REVISION HISTORY SPECIFICATIONS DUAL SUPPLY CONTINUOUS CURRENT PER CHANNEL, Sx OR D ABSOLUTE MAXIMUM RATINGS THERMAL RESISTANCE ESD CAUTION PIN CONFIGURATION AND FUNCTION DESCRIPTIONS TRUTH TABLE TYPICAL PERFORMANCE CHARACTERISTICS TEST CIRCUITS TERMINOLOGY THEORY OF OPERATION APPLICATIONS INFORMATION POWER SUPPLY SEQUENCING OUTLINE DIMENSIONS ORDERING GUIDE
Data Sheet ADG798 SPECIFICATIONS
VDD = 5 V ± 10%, VSS = 0 V, GND = 0 V, unless otherwise noted. TSSOP temperature range = −55°C ≤ TA ≤ +175°C and FLATPACK temperature range = −55°C ≤ TA ≤ +210°C, unless otherwise noted.
Table 1. TSSOP FLATPACK Parameter Symbol Test Conditions/Comments1 Min Typ2 Max Min Typ
2
Max Unit
ANALOG SWITCH Analog Signal Range 0 VDD 0 VDD V On Resistance RON VS = 0 V to VDD, IDS = 10 mA; see 4.5 9 5 10 Ω Figure 24 Matching Between ΔRON VS = 0 V to VDD, IDS = 10 mA 0.6 1.2 1.25 1.5 Ω Channels Flatness RFLAT (ON) VS = 0 V to VDD, IDS = 10 mA 1.5 0.75 2 Ω LEAKAGE CURRENTS VDD = 5.5 V Source Off Leakage IS (Off) VD = 4.5 V/1 V, VS = 1 V/4.5 V; see −50 ±0.01 +50 −180 ±0.01 +180 nA Figure 25 Drain Off Leakage ID (Off) VD = 4.5 V/1 V, VS = 1 V/4.5 V; see −650 ±0.01 +650 −2600 ±0.01 +2600 nA Figure 26 Channel On Leakage ID (On), VD = VS = 1 V or 4.5 V; see Figure 27 −650 ±0.01 +650 −2600 ±0.01 +2600 nA IS (On) DIGITAL INPUTS Input Voltage High VINH 2.4 2.4 V Low VINL 0.8 0.8 V Input Current IINL or VIN = VINL or VINH −800 +0.005 +800 −800 +0.005 +800 nA IINH Digital Input Capacitance CIN 2 2 pF DYNAMIC CHARACTERISTICS3 Transition Time tTRANSITION RL = 150 Ω, CL = 15 pF; see 12 21 12 23 ns Figure 28 VS1 = 3 V/0 V, VS8 = 0 V/3 V Break-Before-Make Time tOPEN RL = 150 Ω, CL = 15 pF, VS = 3 V; 1 8 1 8 ns Delay see Figure 29 TA = maximum temperature 9 9 ns On Time tON (EN) RL = 150 Ω, CL = 15 pF 11 17 11 20 ns VS = 3 V; see Figure 30 Off Time tOFF (EN) RL = 150 Ω, CL = 15 pF 5.5 11 5.5 12 ns VS = 3 V; see Figure 30 Charge Injection QINJ VS = 2.5 V, RS = 0 Ω, CL = 1 nF; see ±3 ±3 pC Figure 31 Off Isolation RL = 50 Ω, CL = 5 pF, f = 10 MHz −60 −60 dB RL = 50 Ω, CL = 5 pF, f = 1 MHz; see −80 −80 dB Figure 32 Channel to Channel RL = 50 Ω, CL = 5 pF, f = 10 MHz −60 −60 dB Crosstalk RL = 50 Ω, CL = 5 pF, f = 1 MHz; see −80 −80 dB Figure 33 −3 dB Bandwidth RL = 50 Ω, CL = 5 pF; see Figure 34 55 55 MHz Source Capacitance, Off CS (Off) f = 1 MHz 13 13 pF Rev. A | Page 3 of 22 Document Outline FEATURES APPLICATIONS FUNCTIONAL BLOCK DIAGRAM GENERAL DESCRIPTION PRODUCT HIGHLIGHTS TABLE OF CONTENTS REVISION HISTORY SPECIFICATIONS DUAL SUPPLY CONTINUOUS CURRENT PER CHANNEL, Sx OR D ABSOLUTE MAXIMUM RATINGS THERMAL RESISTANCE ESD CAUTION PIN CONFIGURATION AND FUNCTION DESCRIPTIONS TRUTH TABLE TYPICAL PERFORMANCE CHARACTERISTICS TEST CIRCUITS TERMINOLOGY THEORY OF OPERATION APPLICATIONS INFORMATION POWER SUPPLY SEQUENCING OUTLINE DIMENSIONS ORDERING GUIDE