Datasheet ADGS1412 (Analog Devices)

SPI Interface, 1.5 Ω RON, ±15 V/+12 V, Quad SPST Switch, Mux Configurable Data Sheet ADGS1412 FEATURES FUNCTIONAL BLOCK DIAGRAM SPI interface with error detection ADGS1412 Includes CRC, invalid read/write address, and SCLK count S1 D1 error detection Supports burst mode and daisy-chain mode S2 D2 Industry-standard SPI Mode 0 and Mode 3 interface compatible Guaranteed break-before-make switching allowing external S3 D3 wiring of switches to deliver multiplexer configurations S4 D4 1.5 Ω typical on resistance at 25°C 0.3 Ω typical on resistance flatness at 25°C SPI SDO INTERFACE 0.1 Ω typical on resistance match between channels at 25°C VSS to VDD analog signal range
001
Fully specified at ±15 V, ±5 V, and +12 V SCLK SDI CS RESET/VL
14960-
1.8 V logic compatibility with 2.7 V ≤ VL ≤ 3.3 V
Figure 1.
24-lead LFCSP APPLICATIONS Automated test equipment Data acquisition systems Battery-powered systems Sample-and-hold systems Audio signal routing Video signal routing Communications systems Relay replacement GENERAL DESCRIPTION
The ADGS1412 contains four independent single-pole/single- The on-resistance profile is flat over the full analog input range, throw (SPST) switches. A serial peripheral interface (SPI) which ensures good linearity and low distortion when switching controls the switches. The SPI interface has robust error detection audio signals. features such as cyclic redundancy check (CRC) error detection,
PRODUCT HIGHLIGHTS
invalid read/write address detection, and SCLK count error detection. 1. SPI interface removes the need for paral el conversion, logic traces and reduces general-purpose input/output It is possible to daisy-chain multiple ADGS1412 devices together. (GPIO) channel count. Daisy-chain mode enables the configuration of multiple devices 2. Daisy-chain mode removes additional logic traces when with a minimal amount of digital lines. The ADGS1412 can also multiple devices are used. operate in burst mode to decrease the time between SPI 3. CRC error detection, invalid read/write address detection, commands. and SCLK count error detection ensures a robust digital iCMOS construction ensures ultralow power dissipation, making interface. the device ideally suited for portable and battery-powered 4. CRC and error detection capabilities allow the use of the instruments. ADGS1412 in safety critical systems. Each switch conducts equally wel in both directions when on, 5. Guaranteed break-before-make switching allows the use of and each switch has an input signal range that extends to the the ADGS1412 in multiplexer configurations with external supplies. In the off condition, signal levels up to the supplies wiring. are blocked. 6. Minimum distortion.
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Document Outline FEATURES APPLICATIONS FUNCTIONAL BLOCK DIAGRAM GENERAL DESCRIPTION PRODUCT HIGHLIGHTS TABLE OF CONTENTS REVISION HISTORY SPECIFICATIONS ±15 V DUAL SUPPLY ±5 V DUAL SUPPLY 12 V SINGLE SUPPLY CONTINUOUS CURRENT PER CHANNEL, Sx OR Dx TIMING CHARACTERISTICS Timing Diagrams ABSOLUTE MAXIMUM RATINGS THERMAL RESISTANCE ESD CAUTION PIN CONFIGURATION AND FUNCTION DESCRIPTIONS TYPICAL PERFORMANCE CHARACTERISTICS TEST CIRCUITS TERMINOLOGY THEORY OF OPERATION ADDRESS MODE ERROR DETECTION FEATURES Cyclic Redundancy Check (CRC) Error Detection SCLK Count Error Detection Invalid Read/Write Address Error CLEARING THE ERROR FLAGS REGISTER BURST MODE SOFTWARE RESET DAISY-CHAIN MODE POWER-ON RESET APPLICATIONS INFORMATION BREAK-BEFORE-MAKE SWITCHING DIGITAL INPUT BUFFERS POWER SUPPLY RAILS POWER SUPPLY RECOMMENDATIONS REGISTER SUMMARY REGISTER DETAILS SWITCH DATA REGISTER ERROR CONFIGURATION REGISTER ERROR FLAGS REGISTER BURST ENABLE REGISTER SOFTWARE RESET REGISTER OUTLINE DIMENSIONS ORDERING GUIDE