Datasheet ADG1236 (Analog Devices) - 8
| 制造商 | Analog Devices |
| 描述 | Low Capacitance, Low Charge Injection, ±15 V/12 V iCMOS, Dual SPDT Switch |
| 页数 / 页 | 16 / 8 — ADG1236. Data Sheet. TERMINOLOGY IDD. CD (Off). CD, CS (On). VD (VS). … |
| 修订版 | A |
| 文件格式/大小 | PDF / 351 Kb |
| 文件语言 | 英语 |
ADG1236. Data Sheet. TERMINOLOGY IDD. CD (Off). CD, CS (On). VD (VS). CIN. RON. tTRANS. RFLAT(ON). Charge Injection. IS (Off). ID (Off)
该数据表的模型线
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ADG1236 Data Sheet TERMINOLOGY IDD CD (Off)
The positive supply current. The off switch drain capacitance, measured with reference to
I
ground.
SS
The negative supply current.
CD, CS (On) VD (VS)
The on switch capacitance, measured with reference to ground. The analog voltage on Terminals D and S.
CIN RON
The digital input capacitance. The ohmic resistance between D and S.
tTRANS RFLAT(ON)
The delay time between the 50% and 90% points of the digital Flatness is defined as the difference between the maximum and input and switch on condition when switching from one minimum value of on resistance as measured over the specified address state to another. analog signal range.
Charge Injection IS (Off)
A measure of the glitch impulse transferred from the digital The source leakage current with the switch off. input to the analog output during switching.
ID (Off) Off Isolation
The drain leakage current with the switch off. A measure of unwanted signal coupling through an off switch.
ID, IS (On) Crosstalk
The channel leakage current with the switch on. A measure of unwanted signal that is coupled through from one
V
channel to another as a result of parasitic capacitance.
INL
The maximum input voltage for Logic 0.
Bandwidth V
The frequency at which the output is attenuated by 3 dB.
INH
The minimum input voltage for Logic 1.
On Response I
The frequency response of the on switch.
INL (IINH)
The input current of the digital input.
Insertion Loss C
The loss due to the on resistance of the switch.
S (Off )
The off switch source capacitance, measured with reference to
THD + N
ground. The ratio of the harmonic amplitude plus noise of the signal to the fundamental. Rev. A | Page 8 of 16 Document Outline FEATURES APPLICATIONS FUNCTIONAL BLOCK DIAGRAM GENERAL DESCRIPTION PRODUCT HIGHLIGHTS REVISION HISTORY SPECIFICATIONS DUAL SUPPLY SINGLE SUPPLY ABSOLUTE MAXIMUM RATINGS ESD CAUTION TRUTH TABLE FOR SWITCHES PIN CONFIGURATIONS AND FUNCTION DESCRIPTIONS TERMINOLOGY TYPICAL PERFORMANCE CHARACTERISTICS TEST CIRCUITS OUTLINE DIMENSIONS ORDERING GUIDE
The positive supply current. The off switch drain capacitance, measured with reference to
I
ground.
SS
The negative supply current.
CD, CS (On) VD (VS)
The on switch capacitance, measured with reference to ground. The analog voltage on Terminals D and S.
CIN RON
The digital input capacitance. The ohmic resistance between D and S.
tTRANS RFLAT(ON)
The delay time between the 50% and 90% points of the digital Flatness is defined as the difference between the maximum and input and switch on condition when switching from one minimum value of on resistance as measured over the specified address state to another. analog signal range.
Charge Injection IS (Off)
A measure of the glitch impulse transferred from the digital The source leakage current with the switch off. input to the analog output during switching.
ID (Off) Off Isolation
The drain leakage current with the switch off. A measure of unwanted signal coupling through an off switch.
ID, IS (On) Crosstalk
The channel leakage current with the switch on. A measure of unwanted signal that is coupled through from one
V
channel to another as a result of parasitic capacitance.
INL
The maximum input voltage for Logic 0.
Bandwidth V
The frequency at which the output is attenuated by 3 dB.
INH
The minimum input voltage for Logic 1.
On Response I
The frequency response of the on switch.
INL (IINH)
The input current of the digital input.
Insertion Loss C
The loss due to the on resistance of the switch.
S (Off )
The off switch source capacitance, measured with reference to
THD + N
ground. The ratio of the harmonic amplitude plus noise of the signal to the fundamental. Rev. A | Page 8 of 16 Document Outline FEATURES APPLICATIONS FUNCTIONAL BLOCK DIAGRAM GENERAL DESCRIPTION PRODUCT HIGHLIGHTS REVISION HISTORY SPECIFICATIONS DUAL SUPPLY SINGLE SUPPLY ABSOLUTE MAXIMUM RATINGS ESD CAUTION TRUTH TABLE FOR SWITCHES PIN CONFIGURATIONS AND FUNCTION DESCRIPTIONS TERMINOLOGY TYPICAL PERFORMANCE CHARACTERISTICS TEST CIRCUITS OUTLINE DIMENSIONS ORDERING GUIDE