Datasheet ADG633 (Analog Devices) - 3

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Data Sheet ADG633 SPECIFICATIONS DUAL-SUPPLY OPERATION
VDD = +5 V, VSS = −5 V, GND = 0 V, TA = −40°C to +125°C, unless otherwise noted.
Table 1. Parameter +25°C −40°C to +85°C −40°C to +125°C Unit Test Conditions/Comments
ANALOG SWITCH Analog Signal Range VSS to VDD V VDD = +4.5 V, VSS = −4.5 V On Resistance, RON 52 Ω typ VS = ±4.5 V, IS = 1 mA; see Figure 20 75 90 100 Ω max VS = ±4.5 V, IS = 1 mA; see Figure 20 On-Resistance Match 0.8 Ω typ VS = +3.5 V, IS = 1 mA Between Channels, ΔRON 1.3 1.8 2 Ω max VS = +3.5 V, IS = 1 mA On-Resistance Flatness, RFLAT(ON) 9 Ω typ VDD = +5 V, VSS = −5 V, VS = ±3 V, IS = 1 mA 12 13 14 Ω max VDD = +5 V, VSS = −5 V, VS = ±3 V, IS = 1 mA LEAKAGE CURRENTS VDD = +5.5 V, VSS = −5.5 V Source Off Leakage, IS(OFF) ±0.005 nA typ VD = ±4.5 V, VS = +4.5 V; see Figure 21 ±0.2 ±5 nA max VD = ±4.5 V, VS = +4.5 V; see Figure 21 Drain Off Leakage, ID(OFF) ±0.005 nA typ VD = ±4.5 V, VS = + 4.5 V; see Figure 22 ±0.2 ±5 nA max VD = ±4.5 V, VS = + 4.5 V; see Figure 22 Channel On Leakage, ID(ON), IS(ON) ±0.005 nA typ VD = VS = ±4.5 V; see Figure 23 ±0.2 ±5 nA max VD = VS = ±4.5 V; see Figure 23 DIGITAL INPUTS Input High Voltage, VINH 2.4 V min Input Low Voltage, VINL 0.8 V max Input Current, IINL or IINH 0.005 μA typ VIN = VINL or VINH ±1 μA max VIN = VINL or VINH Digital Input Capacitance, CIN 2 pF typ DYNAMIC CHARACTERISTICS1 tTRANSITION 60 ns typ RL = 300 Ω, CL = 35 pF, VS = 3 V; see Figure 24 90 110 130 ns max RL = 300 Ω, CL = 35 pF, VS = 3 V; see Figure 24 tON (EN) 70 ns typ RL = 300 Ω, CL = 35 pF, VS = 3 V; see Figure 26 95 120 135 ns max RL = 300 Ω, CL = 35 pF, VS = 3 V; see Figure 26 tOFF (EN) 25 ns typ RL = 300 Ω, CL = 35 pF, VS = 3 V; see Figure 26 40 45 50 ns max RL = 300 Ω, CL = 35 pF, VS = 3 V; see Figure 26 Break-Before-Make Time Delay, tBBM 40 ns typ RL = 300 Ω, CL = 35 pF, VS1 = VS2 = 3 V; see Figure 25 10 ns min RL = 300 Ω, CL = 35 pF, VS1 = VS2 = 3 V; see Figure 25 Charge Injection 2 pC typ VS = 0 V, RS = 0 Ω, CL = 1 nF; see Figure 27 4 pC max VS = 0 V, RS = 0 Ω, CL = 1 nF; see Figure 27 Off Isolation −90 dB typ RL = 50 Ω, CL = 5 pF, f = 1 MHz; see Figure 28 Total Harmonic Distortion, THD + N 0.025 % typ RL = 600 Ω, 2 V p-p, f = 20 Hz to 20 kHz Channel-to-Channel Crosstalk −90 dB typ RL = 50 Ω, CL = 5 pF, f = 1 MHz; see Figure 30 −3 dB Bandwidth 580 MHz typ RL = 50 Ω, CL = 5 pF; see Figure 29 CS(OFF) 4 pF typ f = 1 MHz CD(OFF) 7 pF typ f = 1 MHz CD(ON), CS(ON) 12 pF typ f = 1 MHz POWER REQUIREMENTS2 VDD = +5.5 V, VSS = −5.5 V IDD 0.01 μA typ Digital inputs = 0 V or 5.5 V 1 μA max Digital inputs = 0 V or 5.5 V ISS 0.01 μA typ Digital inputs = 0 V or 5.5 V 1 μA max Digital inputs = 0 V or 5.5 V 1 Guaranteed by design; not subject to production test. 2 The device is fully specified at a ±5 V dual supply and at 5 V and 3.3 V single supplies. It is possible to operate the ADG633 with unbalanced supplies or at other voltage supplies ( ±2 V to ±6 V, and 2 V to 12 V); however, the switch characteristics change. These changes include, but are not limited to: analog signal range, on resistance, leakage, VINL, VINH, and switching times. The optimal power-up sequence for the device is: ground, VDD, VSS, and then the digital inputs, before applying the analog input signal. Rev. B | Page 3 of 16 Document Outline FEATURES APPLICATIONS FUNCTIONAL BLOCK DIAGRAM GENERAL DESCRIPTION PRODUCT HIGHLIGHTS TABLE OF CONTENTS REVISION HISTORY SPECIFICATIONS DUAL-SUPPLY OPERATION SINGLE-SUPPLY OPERATION ABSOLUTE MAXIMUM RATINGS ESD CAUTION PIN CONFIGURATIONS AND FUNCTION DESCRIPTIONS TYPICAL PERFORMANCE CHARACTERISTICS TERMINOLOGY TEST CIRCUITS OUTLINE DIMENSIONS ORDERING GUIDE NOTES NOTES