Datasheet ADG725, ADG731 (Analog Devices) - 5

ADG725/ADG731 TIMING CHARACTERISTICS1, 2 Parameter Limit at TMIN, TMAX Unit Conditions/Comments
fSCLK 30 MHz max SCLK Cycle Frequency t1 33 ns min SCLK Cycle Time t2 13 ns min SCLK High Time t3 13 ns min SCLK Low Time t4 13 ns min SYNC to SCLK Falling Edge Setup Time t5 40 ns min Minimum SYNC Low Time t6 5 ns min Data Setup Time t7 4.5 ns min Data Hold Time t8 33 ns min Minimum SYNC High Time NOTES 1See Figure 1. 2All input signals are specified with tr = tf = 5 ns (10% to 90% of VDD) and timed from a voltage level of (VIL + VIH)/2. Specifications subject to change without notice.
t1 SCLK t2 t3 t t 8 4 t5 SYNC t7 t6 DIN DB7 DB0
Figure 1. 3-Wire Serial Interface Timing Diagram
DB7 (MSB) DB0 (LSB) DB7 (MSB) DB0 (LSB) A3 A2 A1 A0 EN CSA CSB X A4 A3 A2 A1 A0 EN CS X DATA BITS DATA BITS
Figure 2. ADG725 Input Shift Register Contents Figure 3. ADG731 Input Shift Register Contents REV. B –5–