Datasheet ADG725, ADG731 (Analog Devices) - 7

ADG725/ADG731 PIN CONFIGURATIONS 48-Lead LFCSP and TQFP ,C ,C ,C ,C ,C S13A S14A S15A S16A N DA N DB S16B S15B S14B S13B S13 S14 S15 S16 N D N N S32 S31 S30 S29 48 47 46 45 44 43 42 41 40 39 38 37 48 47 46 45 44 43 42 41 40 39 38 37 S12A 1 36 S12B S12 1 36 S28 PIN 1 PIN 1 S11A 2 35 IDENTIFIER S11B S11 2 35 IDENTIFIER S27 S10A 3 34 S10B S10 3 34 S26 S9A 4 33 S9B S9 4 33 S25 S8A 5 32 S8B S8 5 32 S24 S7A 6 ADG725 31 S7B S7 6 ADG731 31 S23 TOP VIEW TOP VIEW S6A 7 30 S6B S6 7 30 (Not to Scale) (Not to Scale) S22 S5A 8 29 S5B S5 8 29 S21 S4A 9 28 S4B S4 9 28 S20 S3A 10 27 S3B S3 10 27 S19 S2A 11 26 S2B S2 11 26 S18 S1A 12 25 S1B S1 12 25 S17 13 14 15 16 17 18 19 20 21 22 23 24 13 14 15 16 17 18 19 20 21 22 23 24 DD DD ,C ,C ,C ,C ,C SS N DD DD ,C ,C ,C ,C ,C SS V V N N DIN N N V GND V V N N DIN N N N V SYNC SCLK SYNC GND SCLK N,C = NO7 ,17(51$//<CONNECT(' N,C = NO7,17(51$//< CONNECT 7+((;326('3$',6&211(&7(',17(51$//< )25,1&5($6('5(/,$%,/,7<2)7+(62/'(5 -2,176$1'0$;,0807+(50$/&$3$%,/,7<,7 ,65(&200(1'('7+$77+(3$'%( 62/'(5('727+(68%675$7(,966 PIN FUNCTION DESCRIPTIONS ADG725 ADG731 Mnemonic Function
1–12, 25–40, 1–12, 25–40, Sxx Source. May be an input or output. 45–48 45–48 13, 14 13, 14 VDD Power Supply Input. These parts can be operated from a single supply of 1.8 V to 5.5 V and a dual supply of ± 2.5 V. 17 17 SYNC Active Low Control Input. This is the frame synchronization signal for the input data. When SYNC goes low, it powers on the SCLK and DIN buffers and the input Shift Register is enabled. An 8-bit counter is also enabled. Data is transferred on the falling edges of the following clocks. After eight falling clock edges, switch conditions are automatically updated. SYNC may be used to frame the signal or just pulled low for a short period of time to enable the counter and input buffers. 18 18 DIN Serial Data Input. Data is clocked into the 8-bit Input Register MSB first on the falling edge of the serial clock input. 19 19 SCLK Serial Clock Input. Data is clocked into the Input Shift Register on the falling edge of the serial clock input. These devices can accommodate serial input rates of up to 30 MHz. 23 23 GND Ground Reference 24 24 VSS Most Negative Power Supply in a Dual-Supply Application. In single-supply applications, connect to GND. 41, 43 N/A DA, DB Drain. May be an input or output. N/A 43 D Drain. May be an input or output. &1"% &YQPTFE1BEGPS-'$415IFFYQPTFEQBEJTDPOOFDUFEJOUFSOBMMZ'PSJODSFBTFESFMJBCJMJUZ PGUIFTPMEFSKPJOUTBOENBYJNVNUIFSNBMDBQBCJMJUZ JUJTSFDPNNFOEFEUIBUUIFQBECF TPMEFSFEUPUIFTVCTUSBUF 744 REV. B –7–