Datasheet ADG706, ADG707 (Analog Devices) - 6

制造商Analog Devices
描述CMOS, +1.8 V to +5.5 V/ⴞ2.5 V, 2.5 ⍀ Low-Voltage, 8-/16-Channel Multiplexers
页数 / 页12 / 6 — ADG706/ADG707. Table I. ADG706 Truth Table. Table II. ADG707 Truth Table. …
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ADG706/ADG707. Table I. ADG706 Truth Table. Table II. ADG707 Truth Table. ON Switch. ON Switch Pair. TERMINOLOGY

ADG706/ADG707 Table I ADG706 Truth Table Table II ADG707 Truth Table ON Switch ON Switch Pair TERMINOLOGY

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ADG706/ADG707 Table I. ADG706 Truth Table Table II. ADG707 Truth Table A3 A2 A1 A0 EN ON Switch A2 A1 A0 EN ON Switch Pair
X X X X 0 NONE X X X 0 NONE 0 0 0 0 1 1 0 0 0 1 1 0 0 0 1 1 2 0 0 1 1 2 0 0 1 0 1 3 0 1 0 1 3 0 0 1 1 1 4 0 1 1 1 4 0 1 0 0 1 5 1 0 0 1 5 0 1 0 1 1 6 1 0 1 1 6 0 1 1 0 1 7 1 1 0 1 7 0 1 1 1 1 8 1 1 1 1 8 1 0 0 0 1 9 X = Don’t Care 1 0 0 1 1 10 1 0 1 0 1 11 1 0 1 1 1 12 1 1 0 0 1 13 1 1 0 1 1 14 1 1 1 0 1 15 1 1 1 1 1 16 X = Don’t Care
TERMINOLOGY
VDD Most positive power supply potential CD (OFF) “OFF” Switch drain capacitance. Measured with reference to ground. VSS Most negative power supply in a dual-supply application. In single-supply applications, this CD, CS (ON) “ON” Switch capacitance. Measured with should be tied to ground at the device. reference to ground. IDD Positive supply current CIN Digital input capacitance ISS Negative supply current tTRANSITION Delay time measured between the 50% and 90% points of the digital inputs and the switch GND Ground (0 V) reference “ON” condition when switching from one S Source terminal. May be an input or output. address state to another D Drain terminal. May be an input or output. tON (EN) Delay time between the 50% and 90% points AX Logic control input of the EN digital input and the Switch “ON” condition EN Active high device enable tOFF (EN) Delay time between the 50% and 90% points VD (VS) Analog voltage on terminals D, S of the EN digital input and the Switch “OFF” RON Ohmic resistance between D and S condition ∆RON ON Resistance match between any two channels, tOPEN “OFF” Time measured between the 80% points i.e., RONmax – RONmin of both switches when switching from one address state to another RFLAT(ON) Flatness is defined as the difference between the maximum and minimum value of ON resistance Charge Measure of the glitch impulse transferred from as measured over the specified analog signal Injection the digital input to the analog output during range. switching IS (OFF) Source leakage current with the Switch “OFF” OFF Isolation Measure of unwanted signal coupling through an “OFF” switch ID (OFF) Drain leakage current with the Switch “OFF” Crosstalk Measure of unwanted signal that is coupled ID, IS (ON) Channel leakage current with the Switch “ON” through from one channel to another as a result VINL Maximum input voltage for Logic “0” of parasitic capacitance VINH Minimum input voltage for Logic “1” Bandwidth Frequency at which the output is attenuated IINL(IINH) Input current of the digital input by 3 dB CS (OFF) “OFF” Switch Source Capacitance. Measured ON Response Frequency response of the “ON” Switch with reference to ground. Insertion Loss due to the ON Resistance of Loss the switch –6– REV. B