Datasheet ADG528F (Analog Devices) - 10

ADG528F TERMINOLOGY V tON (EN) DD
Most positive power supply potential. Delay time between the 50% and 90% points of the digital input and switch on condition.
VSS
Most negative power supply potential.
tOFF (EN)
Delay time between the 50% and 90% points of the digital input
GND
and switch off condition. Ground (0 V) reference.
tTRANSITION RON
Delay time between the 50% and 90% points of the digital Ohmic resistance between D and S. inputs and the switch on condition when switching from one
RON Drift
address state to another. Change in RON when temperature changes by one degree
tOPEN
Celsius. Off time measured between 80% points of both switches when
RON Match
switching from one address state to another. Difference between the RON of any two channels.
VINL IS (Off)
Maximum input voltage for Logic 0. Source leakage current when the switch is off.
VINH ID (Off)
Minimum input voltage for Logic 1. Drain leakage current when the switch is off.
IINL (IINH) ID, IS (On)
Input current of the digital input. Channel leakage current when the switch is on.
Off Isolation VD (VS)
A measure of unwanted signal coupling through an off channel. Analog Voltage on Terminal D and Terminal S.
Charge Injection CS (Off)
A measure of the glitch impulse transferred from the digital Channel input capacitance for off condition. input to the analog output during switching.
CD (Off) IDD
Channel output capacitance for off condition. Positive supply current.
CD, CS (On) ISS
On switch capacitance. Negative supply current.
CIN
Digital input capacitance. Rev. F | Page 10 of 16 Document Outline FEATURES APPLICATIONS FUNCTIONAL BLOCK DIAGRAM GENERAL DESCRIPTION PRODUCT HIGHLIGHTS TABLE OF CONTENTS REVISION HISTORY SPECIFICATIONS DUAL SUPPLY TRUTH TABLE TIMING DIAGRAMS ABSOLUTE MAXIMUM RATINGS ESD CAUTION PIN CONFIGURATION AND FUNCTION DESCRIPTIONS TYPICAL PERFORMANCE CHARACTERISTICS TERMINOLOGY THEORY OF OPERATION TEST CIRCUITS OUTLINE DIMENSIONS ORDERING GUIDE