Datasheet ADG431, ADG432, ADG433 (Analog Devices) - 6

ADG431/ADG432/ADG433 120 VG VG V V V S D V V S D DD = +15V VSS = –15V VL = +5V 100 T P-CHANNEL T N-CHANNEL T P+ P+ N+ N+ R R R dB E E E – N N N C C C H H P– N– H 80 BURIED OXIDE LAYER SUBSTRATE (BACKGATE) OFF ISOLATION 60
Figure 1. Trench Isolation
APPLICATION 40
Figure 2 illustrates a precise, fast sample-and-hold circuit.
100 1k 10k 100k 1M 10M FREQUENCY – Hz
An AD845 is used as the input buffer while the output opera- tional amplifier is an AD711. During the track mode, SW1 is TPC 7. Off Isolation vs. Frequency closed and the output VOUT follows the input signal VIN. In the hold mode, SW1 is opened and the signal is held by the hold capacitor CH.
110
Due to switch and capacitor leakage, the voltage on the hold
VDD = +15V
capacitor will decrease with time. The ADG431/ADG432/
VSS = –15V 100 V
ADG433 minimizes this droop due to its low leakage specifica-
L = +5V
tions. The droop rate is further minimized by the use of a polystyrene hold capacitor. The droop rate for the circuit
dB – 90
shown is typically 30 µV/µs. A second switch SW2, which operates in parallel with SW1, is
80
included in this circuit to reduce pedestal error. Since both
CROSSTALK
switches will be at the same potential, they will have a differen- tial effect on the op amp AD711 which will minimize charge
70
injection effects. Pedestal error is also reduced by the compensa- tion network RC and CC. This compensation network also reduces the hold time glitch while optimizing the acquisition time. Using
60100 1k 10k 100k 1M 10M
the illustrated op amps and component values, the pedestal error
FREQUENCY – Hz
has a maximum value of 5 mV over the ± 10 V input range. Both TPC 8. Crosstalk vs. Frequency the acquisition and settling times are 850 ns.
TRENCH ISOLATION +15V +5V
In the ADG431A, ADG432A and ADG433A, an insulating
2200pF
oxide layer (trench) is placed between the NMOS and PMOS
+15V SW2
transistors of each CMOS switch. Parasitic junctions, which
+15V S D C
occur between the transistors in junction isolated switches, are
R C C V AD711 IN 1000pF VOUT SW1 75
eliminated, the result being a completely latch-up proof switch.
AD845 S D CH –15V
In junction isolation, the N and P wells of the PMOS and NMOS
2200pF –15V
transistors from a diode that is reverse-biased under normal
ADG431
operation. However, during overvoltage conditions, this diode
ADG432 ADG433
becomes forward biased. A silicon-controlled rectifier (SCR) type circuit is formed by the two transistors causing a significant
–15V
amplification of the current which, in turn, leads to latch up. With trench isolation, this diode is removed, the result being a Figure 2. Fast, Accurate Sample-and-Hold latch-up proof switch. –6– REV. C