Datasheet ADG411, ADG412, ADG413 (Analog Devices) - 10

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ADG411/ADG412/ADG413 APPLICATIONS
Figure 13 illustrates a precise, fast, sample-and-hold circuit. An the hold time glitch while optimizing the acquisition time. AD845 is used as the input buffer while the output operational Using the illustrated op amps and component values, the amplifier is an AD711. During the track mode, SW1 is closed pedestal error has a maximum value of 5 mV over the ±10 V and the output VOUT follows the input signal VIN. In the hold input range. Both the acquisition and settling times are 850 ns. mode, SW1 is opened and the signal is held by the hold
+15V +5V
capacitor CH.
2200pF
Due to switch and capacitor leakage, the voltage on the hold
+15V SW1
capacitor decreases with time. The ADG411/ADG412/ADG413
+15V S D C R C C AD711 V
minimizes this droop due to its low leakage specifications. The
VIN SW2 1000pF OUT 75
Ω
AD845
droop rate is further minimized by the use of a polystyrene
S D CH –15V
hold capacitor. The droop rate for the circuit shown is typically
2200pF –15V ADG411
30 μV/μs.
ADG412 ADG413
A second switch, SW2, which operates in parallel with SW1, is 013 included in this circuit to reduce pedestal error. Since both 00024-
–15V
switches are at the same potential, they have a differential effect Figure 13. Fast, Accurate Sample-and-Hold on the op amp AD711, which minimizes charge injection effects. Pedestal error is also reduced by the compensation network RC and CC. This compensation network also reduces Rev. D | Page 10 of 16 Document Outline FEATURES APPLICATIONS GENERAL DESCRIPTION PRODUCT HIGHLIGHTS FUNCTIONAL BLOCK DIAGRAMS REVISION HISTORY SPECIFICATIONS DUAL SUPPLY SINGLE SUPPLY ABSOLUTE MAXIMUM RATINGS ESD CAUTION PIN CONFIGURATION AND FUNCTION DESCRIPTIONS TYPICAL PERFORMANCE CHARACTERISTICS TERMINOLOGY APPLICATIONS TEST CIRCUITS OUTLINE DIMENSIONS ORDERING GUIDE