Datasheet AD9696, AD9698 (Analog Devices) - 5

AD9696/AD9698 LATCH ENABLE LATCH TWO DIODES COMPARE ABOVE GROUND VOS tPW (E) tH tS DIFFERENTIAL VIN INPUT VOLTAGE VOD Q 50% tPD tPD (E) Q 50% tS – MINIMUM SETUP TIME (Typically 1.7ns) tPW (E) – MINIMUM LATCH ENABLE PULSE WIDTH (Typically 2.5ns) t H – MINIMUM HOLD TIME (Typically 1.9ns) VOS – INPUT OFFSET VOLTAGE t PD – INPUT TO OUTPUT DELAY V – OVERDRIVE VOLTAGE OD t – LATCH ENABLE TO OUTPUT DELAY PD (E)
AD9696/AD9698 Timing Diagram
THEORY OF OPERATION DIE LAYOUT AND MECHANICAL INFORMATION
Die Dimensions AD9696 . 59×71×15 (± 2) mils Refer to the block diagram of the AD9696/AD9698 compara- AD9698 . 79×109×15 (± 2) mils tors. The AD9696 and AD9698 TTL voltage comparator archi- Pad Dimensions . 4×4 mils tecture consists of five basic stages: input, latch, gain, level shift Metalization . Aluminum and output. Each stage is designed to provide optimal perfor- Backing . None mance and make it easy to use the comparators. Substrate Potential . –VS The input stage operates with either a single +5-volt supply, or Passivation . Nitride with a +5-volt supply and a –5.2-volt supply. For optimum power efficiency, the remaining stages operate with only a single +5-volt supply. The input stage is an input differential pair without the customary emitter follower buffers. This configura- tion increases input bias currents but maximizes the input volt- age range. A latch stage allows the most recent output state to be retained as long as the latch input is held high. In this way, the input to the comparator can be changed without any change in the out- put state. As soon as the latch enable input is switched to LOW, the output changes to the new value dictated by the signal ap- plied to the input stage. The gain stage assures that even with small values of input volt- age, there will be sufficient levels applied to the following stages to cause the output to switch TTL states as required. A level shift stage between the gain stage and the TTL output stage guarantees that appropriate voltage levels are applied from the gain stage to the TTL output stage. Only the output stage uses TTL logic levels; this minimum use of TTL circuits maximizes speed and minimizes power con- sumption. The outputs are clamped with Schottky diodes to as- sure that the rising and falling edges of the output signal are closely matched. The AD9696 and AD9698 represent the state of the art in high speed TTL voltage comparators. Great care has been taken to optimize the propagation delay dispersion performance. This as- sures that the output delays will remain constant despite varying levels of input overdrive. This characteristic, along with closely matched rising and falling outputs, provides extremely consis- tent results at previously unattainable speeds. REV. B –5–