Datasheet NCV5230 (ON Semiconductor) - 6

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NCV5230 Output Stage
combined voltages across diodes D1 and D2 are Processing output voltage swings that nominally reach to proportional to the logarithm of the square of the reference less than 100 mV of either supply voltage can only be current IB1. When the diode characteristics and achieved by a pair of complementary common−emitter temperatures of the pairs Q1, D1 and Q3, Q2 are equal, the connected transistors. Normally, such a configuration relation IOP × ION − IB1 × IB1 is satisfied. causes complex feed−forward signal paths that develop by Separating the functions of biasing and driving prevents combining biasing and driving which can be found in the driving signals from becoming delayed by the biasing previous low supply voltage designs. The unique output circuit. The output Darlington transistors are directly stage of the NCV5230 separates the functions of driving and accessible for in−phase driving signals on the bases of Q5 biasing, as shown in the simplified schematic of Figure 2 and and Q2. This is very important for simple high−frequency has the advantage of a shorter signal path which leads to compensation. The output transistors can be high−frequency increasing the effective bandwidth. compensated by Miller capacitors CM1A and CM1B This output stage consists of two parts: the Darlington connected from the collectors to the bases of the output output transistors and the class AB control regulator. The Darlington transistors. output transistor Q3 connected with the Darlington A general−purpose op amp of this type must have enough transistors Q4 and Q5 can source up to 10 mA to an output open−loop gain for applications when the output is driving load. The output of NPN Darlington connected transistors a low resistance load. The NCV5230 accomplishes this by Q1 and Q2 together are able to sink an output current of inserting an intermediate common−emitter stage between 10 mA. Accurate and efficient class AB control is necessary the input and output stages. The three stages provide a very to insure that none of the output transistors are ever large gain, but the op amp now has three natural dominant completely cut off. This is accomplished by the differential poles − one at the output of each common−emitter stage. amplifier (formed by Q8 and Q9) which controls the biasing Frequency compensation is implemented with a simple of the output transistors. The differential amplifier compares scheme of nested, pole−splitting Miller integrators. The the summed voltages across two diodes, D1 and D2, at the Miller capacitors CM1A and CM1B are the first part of the base of Q8 with the summed voltages across the nested structure, and provide compensation for the output base−emitter diodes of the output transistors Q1 and Q3. The and intermediate stages. A second pair of Miller integrators base−emitter voltage of Q3 is converted into a current by Q6 provide pole−splitting compensation for the pole from the and R6 and reconverted into a voltage across the input stage and the pole resulting from the compensated base−emitter diode of Q7 and R7. The summed voltage combination of poles from the intermediate and output across the base−emitter diodes of the output transistors Q3 stages. The result is a stable, internally−compensated op and Q1 is proportional to the logarithm of the product of the amp with a phase margin of 70°. push and pull currents IOP and ION, respectively. The VCC R6 Ib1 Ib2 Ib3 Q6 Q3 Vb5 Q5 IOP CM1B Q4 VOUT CM1A V Q2 b2 ION Q8 Q9 D1 R7 I Q7 Q1 b4 Ib5 D2 VEE
Figure 2. Output Stage www.onsemi.com 6