Datasheet MTP3N60E (ON Semiconductor) - 6

制造商ON Semiconductor
描述TMOS E−FET High Energy Power FET N−Channel Enhancement−Mode Silicon Gate
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MTP3N60E. SAFE OPERATING AREA INFORMATION. Figure 7. Maximum Rated Forward Biased. Figure 8. Maximum Rated Switching

MTP3N60E SAFE OPERATING AREA INFORMATION Figure 7 Maximum Rated Forward Biased Figure 8 Maximum Rated Switching

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MTP3N60E

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MTP3N60E SAFE OPERATING AREA INFORMATION
100 16 VGS = 20 V SINGLE PULSE TC = 25°C 10 μs 12 (AMPS) 10 (AMPS) 100 μs 1 ms 10 ms 8 dc 1 TJ ≤ 150°C , DRAIN CURRENT , DRAIN CURRENT I D I D 4 RDS(on) LIMIT THERMAL LIMIT PACKAGE LIMIT 0 0.1 1 10 100 1000 0 200 400 600 80 V V DS, DRAIN−TO−SOURCE VOLTAGE (VOLTS) DS, DRAIN−TO−SOURCE VOLTAGE (VOLTS)
Figure 7. Maximum Rated Forward Biased Figure 8. Maximum Rated Switching Safe Operating Area Safe Operating Area
The power averaged over a complete switching cycle must be less than:
FORWARD BIASED SAFE OPERATING AREA
The FBSOA curves define the maximum drain−to−source TJ(max) − TC voltage and drain current that a device can safely handle RθJC when it is forward biased, or when it is on, or being turned 10000 on. Because these curves include the limitations of VDD = 300 V simultaneous high voltage and high current, up to the rating ID = 3 A of the device, they are especially useful to designers of VGS(on) = 10 V td(off) linear systems. The curves are based on a case TJ = 25°C 1000 temperature of 25°C and a maximum junction temperature of 150°C. Limitations for repetitive pulses at various case (ns) temperatures can be determined by using the thermal tf td(on) response curves. Motorola Application Note, AN569, t, TIME “Transient Thermal Resistance−General Data and Its Use” 100 provides detailed instructions. tr
SWITCHING SAFE OPERATING AREA
The switching safe operating area (SOA) of Figure 8 is 10 the boundary that the load line may traverse without 1 10 100 100 incurring damage to the MOSFET. The fundamental limits RG, GATE RESISTANCE (OHMS) are the peak current, IDM and the breakdown voltage,
Figure 9. Resistive Switching Time
V(BR)DSS. The switching SOA shown in Figure 8 is
Variation versus Gate Resistance
applicable for both turn−on and turn−off of the devices for switching times less than one microsecond.
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