Preliminary Datasheet EPC23102 (Efficient Power Conversion)

eGaN® FET DATASHEET
EPC23102
EPC23102 – ePower™ Stage IC
VIN , 100 V
EFFICIENT POWER CONVERSION
ILoad , 35 A
PRELIMINARY HAL
The ePowerTM Stage IC Product Family integrates input logic interface, level shifting, bootstrap charging and gate drive buffer circuits along with eGaN output FETs. Integration is implemented using EPC’s proprietary GaN IC technology. The end result is a Power Stage IC that translates logic level input to
EPC
high voltage and high current power output that is smaller in size, easier to manufacture, simpler to
23102 CYYWWE
design and more efficient to operate.
123456 Key Parameters PARAMETER VALUE UNIT
Power Stage Load Current (1 MHz) 35 A
EPC23102 ePowerTM Stage IC
Operating PWM Frequency (Minimum) 5 kHz Package size: 3.5 x 5 mm Operating PWM Frequency (Maximum) 3 MHz Absolute Maximum Input Voltage 100
Applications
Operating Input Voltage Range 80 V • Buck, Boost, Buck-Boost Converters Nominal Bias Supply Voltage 5 • Half-Bridge, Full Bridge LLC Converters Output Current and PWM Frequency Ratings are specified at ambient temperature of 25°C. See Application Information • Motor Drive Inverter section for rating methodologies, test conditions, thermal management techniques and thermal derating curves. • Class D Audio Amplifier
Features Device Information
• Integrated high side and low side eGaN® FET with
PART NUMBER Rated RDS(on) for HS and LS FETs at 25 °C QFN Package Size (mm)
internal gate driver and level shifter
EPC23102
6.6 mΩ + 6.6 mΩ 3.5 x 5 • 5 V external bias supply All exposed pads feature wettable flanks that al ow side wall solder inspection. High voltage and low voltage pads • 3.3 V or 5 V CMOS input logic levels are separated by 0.6mm spacing to meet IPC rules. • Independent high side and low side control inputs
Figure 1: Performance Curves
• Logic lockout commands both FETs off when inputs are both high at same time 98 40 • External resistors to tune SW switching times and 97 35 over-voltage spikes above rail and below ground • Robust level shifter operating for hard and soft 96 30 switching conditions • False trigger immunity from fast switching transients 95 25 • Synchronous charging for high side bootstrap supply 94 20 • Disable input engages low quiescent current mode from VDRV supply
Efficiency (%)
93 15 • Power on reset for low side VDD supply
500 kHz
• Undervoltage lockout for high side V 92
Total Power Loss (W)
10 BOOT supply
1.0 MHz
• Active gate pul -down for HS FET and LS FET with loss 91
1.5 MHz
5 of VDRV supply • Thermal y enhanced QFN 90 0 package with exposed top 0 5 10 15 20 25 30 35 40 for low thermal resistance
I (A) LOAD
from junction to top-side Buck Converter, V heatsink IN = 48 V, VOUT = 12 V, Deadtime = 10 ns, L = 2.2 µH, DCR = 700 µΩ, Top Side Heatsink attached, Airflow = 500 LFM, TA = 25°C, using
EPC90147 Evaluation Board
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