Datasheet MAX6369, MAX6370, MAX6371, MAX6372, MAX6373, MAX6374 (Maxim) - 8

Pin-Selectable Watchdog Timers
to register a logic high while supplying all input current and leakage paths connected to the WDO line. A 10kΩ pull-up is sufficient in most applications. The MAX6370/ MAX6372/MAX6374 have push-pull outputs that pro- START vide an active-low watchdog output pulse of 1ms. When WDO deasserts, timing begins again at the beginning of the watchdog timeout period (Figure 2). SET WDI HIGH
Usage in Noisy Environments
If using the watchdog timer in an electrically noisy envi- PROGRAM ronment, a bypass capacitor of 0.1µF should be con- CODE nected between VCC and GND as close to the device as possible, and no further away than 0.2 inches. POSSIBLE INFINITE LOOP PATH
________________Watchdog Software
SUBROUTINE OR PROGRAM LOOP
Considerations
SET WDI LOW To help the watchdog timer monitor software execution more closely, set and reset the watchdog input at differ-
MAX6369–MAX6374
ent points in the program, rather than pulsing the watch- RETURN dog input high-low-high or low-high-low. This technique avoids a stuck loop, in which the watchdog timer would continue to be reset inside the loop, keeping the watch- dog from timing out. Figure 4 shows an example of a Figure 4. Watchdog Flow Diagram flow diagram where the I/O driving the watchdog input is Selecting 011 (SET2 = 0, SET1 = 1, SET0 = 1) will dis- set high at the beginning of the program, set low at the able the watchdog timer function on all devices in the end of every subroutine or loop, then set high again family. Operation may be reenabled without powering when the program returns to the beginning. If the pro- down by changing the set inputs to the new desired gram should hang in any subroutine, the problem would setting. The device will assume the new selected timing be quickly corrected, since the I/O is continually set low characteristics and enter the startup phase after the and the watchdog timer is allowed to time out, causing 300µs setup time elapses (Figure 3). WDO to pulse. The MAX6373/MAX6374 offer a first-edge feature. In
Pin Configuration
first-edge mode (settings 101 or 110, Table 1), the internal timer does not control the startup delay period. Instead, startup terminates when WDI sees a transition. TOP VIEW If changing to first-edge mode while the device is oper- ating, disable mode must be entered first. It is then safe to select first-edge mode. Entering disable mode first WDI 1 8 VCC ensures the output will be unasserted when selecting MAX6369 first-edge mode and removes the danger of WDI being GND 2 7 WDO MAX6370 masked out. MAX6371 N.C. 3 6 SET2 MAX6372
Output
MAX6373 SET0 4 5 SET1 MAX6374 The MAX6369/MAX6371/MAX6373 have an active-low, open-drain output that provides a watchdog output pulse of 100ms. This output structure will sink current
SOT23-8
when WDO is asserted. Connect a pull-up resistor from WDO to any supply voltage up to +5.5V.
Chip Information
Select a resistor value large enough to register a logic TRANSISTOR COUNT: 1500 low (see Electrical Characteristics), and small enough PROCESS: BiCMOS Maxim cannot assume responsibility for use of any circuitry other than circuitry entirely embodied in a Maxim product. No circuit patent licenses are implied. Maxim reserves the right to change the circuitry and specifications without notice at any time.
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