Datasheet PEMD12, PUMD12 (Nexperia) - 2
| 制造商 | Nexperia |
| 描述 | NPN/PNP Resistor-Equipped Transistors; R1 = 47 kΩ, R2 = 47 kΩ |
| 页数 / 页 | 17 / 2 — PEMD12; PUMD12 NPN/PNP resistor-equipped transistors; R1 = 47 k. , R2 = … |
| 修订版 | 12102022 |
| 文件格式/大小 | PDF / 1.3 Mb |
| 文件语言 | 英语 |
PEMD12; PUMD12 NPN/PNP resistor-equipped transistors; R1 = 47 k. , R2 = 47 k. Rev. 4 — 21 November 2011. Product data sheet
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文件文字版本
PEMD12; PUMD12 NPN/PNP resistor-equipped transistors; R1 = 47 k , R2 = 47 k Rev. 4 — 21 November 2011 Product data sheet 1. Product profile 1.1 General description
NPN/PNP double Resistor-Equipped Transistors (RET) in Surface-Mounted Device (SMD) plastic packages.
Table 1. Product overview Type number Package PNP/PNP NPN/NPN Package complement complement configuration NXP JEITA
PEMD12 SOT666 - PEMB2 PEMH2 ultra small and flat lead PUMD12 SOT363 SC-88 PUMB2 PUMH2 very small
1.2 Features and benefits
100 mA output current capability Reduces component count Built-in bias resistors Reduces pick and place costs Simplifies circuit design AEC-Q101 qualified
1.3 Applications
Low current peripheral driver Control of IC inputs Replaces general-purpose transistors in digital applications
1.4 Quick reference data Table 2. Quick reference data Symbol Parameter Conditions Min Typ Max Unit Per transistor; for the PNP transistor (TR2) with negative polarity
VCEO collector-emitter voltage open base - - 50 V IO output current - - 100 mA R1 bias resistor 1 (input) 33 47 61 k R2/R1 bias resistor ratio 0.8 1 1.2 Document Outline 1. Product profile 1.1 General description 1.2 Features and benefits 1.3 Applications 1.4 Quick reference data 2. Pinning information 3. Ordering information 4. Marking 5. Limiting values 6. Thermal characteristics 7. Characteristics 8. Test information 8.1 Quality information 9. Package outline 10. Packing information 11. Soldering 12. Revision history 13. Legal information 13.1 Data sheet status 13.2 Definitions 13.3 Disclaimers 13.4 Trademarks 14. Contact information 15. Contents
NPN/PNP double Resistor-Equipped Transistors (RET) in Surface-Mounted Device (SMD) plastic packages.
Table 1. Product overview Type number Package PNP/PNP NPN/NPN Package complement complement configuration NXP JEITA
PEMD12 SOT666 - PEMB2 PEMH2 ultra small and flat lead PUMD12 SOT363 SC-88 PUMB2 PUMH2 very small
1.2 Features and benefits
100 mA output current capability Reduces component count Built-in bias resistors Reduces pick and place costs Simplifies circuit design AEC-Q101 qualified
1.3 Applications
Low current peripheral driver Control of IC inputs Replaces general-purpose transistors in digital applications
1.4 Quick reference data Table 2. Quick reference data Symbol Parameter Conditions Min Typ Max Unit Per transistor; for the PNP transistor (TR2) with negative polarity
VCEO collector-emitter voltage open base - - 50 V IO output current - - 100 mA R1 bias resistor 1 (input) 33 47 61 k R2/R1 bias resistor ratio 0.8 1 1.2 Document Outline 1. Product profile 1.1 General description 1.2 Features and benefits 1.3 Applications 1.4 Quick reference data 2. Pinning information 3. Ordering information 4. Marking 5. Limiting values 6. Thermal characteristics 7. Characteristics 8. Test information 8.1 Quality information 9. Package outline 10. Packing information 11. Soldering 12. Revision history 13. Legal information 13.1 Data sheet status 13.2 Definitions 13.3 Disclaimers 13.4 Trademarks 14. Contact information 15. Contents