Datasheet ADuM4165, ADuM4166 (Analog Devices) - 3

link to page 4 link to page 4 link to page 22 link to page 4 link to page 22 Data Sheet
ADuM4165/ADuM4166 SPECIFICATIONS
4.5 V ≤ VBUS1 ≤ 5.5 V, 4.5 V ≤ VBUS2 ≤ 5.5 V, 3.0 V ≤ VDD1 ≤ 3.6 V, and 3.0 V ≤ VDD2 ≤ 3.6 V. All minimum and maximum specifications are applied over the entire recommended operation range, unless otherwise noted. All typical specifications are at TA = 25°C and VDD1 = VDD2 = 3.3 V, unless otherwise noted. Each voltage is relative to its respective ground.
Table 1. Parameter Symbol Min Typ Max Unit Test Conditions/Comments
POWER SUPPLY Supply Current Idle (VDD1, VDD2, VBUS1 or VBUS2)1 UD+, UD−, DD+, and DD− idle Low or Full Speed Mode IDD1(LFI), 21 27 mA IDD2(LFI) High Speed Mode IDD1(HI), 48 60 mA IDD2(HI) Busy (VDD1, VDD2, VBUS1, or VBUS2)2 Low Speed Mode IDD1(L), 29 45 mA Input frequency (fIN) = 750 kHz, load capacitance (CL) = 450 pF IDD2(L) Full Speed Mode IDD1(F), 31 45 mA fIN = 6 MHz, CL = 50 pF IDD2(F) High Speed Mode IDD1(H), 59 70 mA fIN = 240 MHz, CL = 10 pF IDD2(H) Low Power Standby USB suspended or disconnected Upstream (VDD1 or VBUS1) IDD1(S) 1.7 2.5 mA Side 2 not powered 1.7 mA Side 2 powered (average) Downstream (VDD2 and VBUS2) IDD2(S) 20 40 µA VBUS2 = VDD2 = 3 V to 3.6 V, Side 1 not powered 40 100 µA VBUS2 = 4.5 V to 5.5 V, Side 1 not powered 40 µA Side 1 powered (average) VDD2 Maximum Voltage Until After VSTART 3.5 V See the PGOOD, Clock, and Power Sequencing section Side 1 Start-Up Side 1 Start-Up Time t 3 START 3 ms Time after VDD1 rises above VUVLO3+ before VDD2 can be >3.5 V, see the PGOOD, Clock, and Power Sequencing section VBUS1 or VBUS2 Undervoltage Lockout (UVLO) UVLO Threshold, VBUS1 or VBUS2 VUVLO5+ 3.5 4.16 4.35 V Rising UVLO Threshold, VBUS1 or VBUS2 VUVLO5− 3.0 3.77 3.95 V Falling VBUS1 or VBUS2 UVLO Hysteresis VUVLO5HST 0.44 V VDD1 or VDD2 Undervoltage Lockout UVLO Threshold, VDD1 or VDD2 VUVLO3+ 2.4 2.77 2.95 V Rising UVLO Threshold, VDD1 or VDD2 VUVLO3− 2.2 2.60 2.90 V Falling VDD1 or VDD2 UVLO Hysteresis VUVLO3HST 0.18 V LOGIC INPUTS Input Current IIN 0 V ≤ input voltage (VIN) ≤ 3.6 V UD+ and UD− −20 +0.1 +20 µA DD+ and DD− −250 +0.1 +250 µA XI1 and XI2 −30 +0.1 +30 µA Single-Ended Inputs Input Logic High Threshold VIH 2.0 V Input Logic Low Threshold VIL 0.8 V Input Hysteresis VHYS 0.4 V
analog.com Rev. 0 | 3 of 26
Document Outline Features Applications Functional Block Diagrams General Description Specifications Timing Specifications Insulation and Safety Related Specifications Package Characteristics Regulatory Information DIN V VDE V 0884-11 (VDE V 0884-11) Insulation Characteristics (Pending) Recommended Operating Conditions Absolute Maximum Ratings Thermal Resistance Electrostatic Discharge (ESD) Ratings ESD Ratings for ADuM4165/ADuM4166 ESD Caution Pin Configurations and Function Descriptions Truth Tables Typical Performance Characteristics Terminology Bus Upstream and Downstream Hub Host Peripheral Enumeration Low Speed Full Speed High Speed End of Packet (EOP) J State K State SE0 State SE1 State Idle L1 Suspend L2 Suspend Theory of Operation Automatic Data Transfer and Modes Retimer and Other Features Isolator Characteristics and Low Power Modes Applications Information Power Supply Options Clock Options PGOOD, Clock, and Power Sequencing Isolated USB Implementations Peripheral Applications Host Applications Interface Applications PCB Layout and Electromagnetic Interference (EMI) Insulation Lifetime Surface Tracking Insulation Wear Out Calculation and Use of Parameters Example Outline Dimensions Ordering Guide Evaluation Boards