Datasheet MM74C14 (Fairchild)
| 制造商 | Fairchild |
| 描述 | Hex Schmitt Trigger |
| 页数 / 页 | 6 / 1 — MM74C14 He. MM74C14. x Sc. Hex Schmitt Trigger. General Description. t T. … |
| 文件格式/大小 | PDF / 67 Kb |
| 文件语言 | 英语 |
MM74C14 He. MM74C14. x Sc. Hex Schmitt Trigger. General Description. t T. Features. Ordering Code:. Order Number. Package Number
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文件文字版本
MM74C14 He
October 1987 Revised January 1999
MM74C14 x Sc Hex Schmitt Trigger hm General Description
All inputs are protected from damage due to static dis-
i
charge by diode clamps to VCC and GND.
t
The MM74C14 Hex Schmitt Trigger is a monolithic comple-
t T
mentary MOS (CMOS) integrated circuit constructed with
r Features i
N- and P-channel enhancement transistors. The positive
g
and negative going threshold voltages V ■ Wide supply voltage range: 3.0V to 15V
g
T+ and VT−, show
e
low variation with respect to temperature (typ. 0.0005V/°C ■ High noise immunity: 0.70 VCC (typ.)
r
at VCC = 10V), and hysteresis, VT+ − VT− ≥ 0.2 VCC is guar- ■ Low power: TTL compatibility: anteed. 0.4 VCC (typ.) 0.2 VCC guaranteed ■ Hysteresis: 0.4 VCC (typ.): 0.2 VCC guaranteed
Ordering Code: Order Number Package Number Package Description
MM74C14M M14A 14-Lead Small Outline Integrated Circuit (SOIC), JEDEC MS-120, 0.150” Narrow MM74C14N N14A 14-Lead Plastic Dual-In-Line Package (PDIP), JEDEC MS-001, 0.300” Wide Devices also available in Tape and Reel. Specify by appending suffix letter “X” to the ordering code.
Connection Diagram Pin Assignments for DIP and SOIC Top View
© 1999 Fairchild Semiconductor Corporation DS005879.prf www.fairchildsemi.com
October 1987 Revised January 1999
MM74C14 x Sc Hex Schmitt Trigger hm General Description
All inputs are protected from damage due to static dis-
i
charge by diode clamps to VCC and GND.
t
The MM74C14 Hex Schmitt Trigger is a monolithic comple-
t T
mentary MOS (CMOS) integrated circuit constructed with
r Features i
N- and P-channel enhancement transistors. The positive
g
and negative going threshold voltages V ■ Wide supply voltage range: 3.0V to 15V
g
T+ and VT−, show
e
low variation with respect to temperature (typ. 0.0005V/°C ■ High noise immunity: 0.70 VCC (typ.)
r
at VCC = 10V), and hysteresis, VT+ − VT− ≥ 0.2 VCC is guar- ■ Low power: TTL compatibility: anteed. 0.4 VCC (typ.) 0.2 VCC guaranteed ■ Hysteresis: 0.4 VCC (typ.): 0.2 VCC guaranteed
Ordering Code: Order Number Package Number Package Description
MM74C14M M14A 14-Lead Small Outline Integrated Circuit (SOIC), JEDEC MS-120, 0.150” Narrow MM74C14N N14A 14-Lead Plastic Dual-In-Line Package (PDIP), JEDEC MS-001, 0.300” Wide Devices also available in Tape and Reel. Specify by appending suffix letter “X” to the ordering code.
Connection Diagram Pin Assignments for DIP and SOIC Top View
© 1999 Fairchild Semiconductor Corporation DS005879.prf www.fairchildsemi.com