Datasheet TPV803, TPV809, TPV810 (3PEAK) - 8
| 制造商 | 3PEAK |
| 描述 | Low Voltage Supervisory Circuit |
| 页数 / 页 | 15 / 8 — TPV803/809/810. Low Voltage Supervisory Circuit. Detailed Description. … |
| 文件格式/大小 | PDF / 708 Kb |
| 文件语言 | 英语 |
TPV803/809/810. Low Voltage Supervisory Circuit. Detailed Description. Overview. Functional Block Diagram
该数据表的模型线
- TPV803L-3STR TPV803L-3TR TPV803M-3STR TPV803M-3TR TPV803R-3STR TPV803R-3TR TPV803S-3STR TPV803S-3TR TPV803T-3STR TPV803T-3TR TPV803V-3STR TPV803V-3TR TPV803W-3STR TPV803W-3TR TPV803Y-3STR TPV803Y-3TR TPV803Z-3STR TPV803Z-3TR
文件文字版本
TPV803/809/810 Low Voltage Supervisory Circuit Detailed Description Overview
The TPV803/809/810 provides supply voltage supervision function. A reset signal is asserted when the supply voltage is below a preset threshold. In addition, the TPV803/809/810 allows supply voltage stabilization with a fixed timeout before the reset de-asserts after the supply voltage rises above the threshold.
Functional Block Diagram Figure 7 Functional Block Diagram Feature Description
The TPV803/809 feature an active-low open-drain or push-pull output. The TPV8810 features an active-high push-pull output. For active-low output, the reset signal is guaranteed to be logic low for VCC down to 1 V. For active-high output, the reset signal is guaranteed to be logic low for VCC down to 1 V. The reset output is asserted when VCC is below the reset threshold (VTH), Reset remains asserted for the duration of the reset active timeout period (tRP) after VCC rises above the reset threshold. Figure 8 shows the reset outputs.
Figure 8 Reset Timing Diagram www.3peakic.com.cn 8 / 15 Rev.A.5
The TPV803/809/810 provides supply voltage supervision function. A reset signal is asserted when the supply voltage is below a preset threshold. In addition, the TPV803/809/810 allows supply voltage stabilization with a fixed timeout before the reset de-asserts after the supply voltage rises above the threshold.
Functional Block Diagram Figure 7 Functional Block Diagram Feature Description
The TPV803/809 feature an active-low open-drain or push-pull output. The TPV8810 features an active-high push-pull output. For active-low output, the reset signal is guaranteed to be logic low for VCC down to 1 V. For active-high output, the reset signal is guaranteed to be logic low for VCC down to 1 V. The reset output is asserted when VCC is below the reset threshold (VTH), Reset remains asserted for the duration of the reset active timeout period (tRP) after VCC rises above the reset threshold. Figure 8 shows the reset outputs.
Figure 8 Reset Timing Diagram www.3peakic.com.cn 8 / 15 Rev.A.5