IRF510 www.vishay.com Vishay Siliconix L VDS Q Vary t G p to obtain 10 V required IAS R D.U.T Q Q G + GS GD V - DD IAS VG 10 V A t 0.01 p Ω Charge Fig. 12a - Unclamped Inductive Test CircuitFig. 13a - Basic Gate Charge Waveform Current regulator Same type as D.U.T. VDS 50 kΩ tp 12 V 0.2 µF V 0.3 µF DD + V D.U.T. DS - VDS VGS 3 mA IAS I I G D Current sampling resistors Fig. 12b - Unclamped Inductive WaveformsFig. 13b - Gate Charge Test Circuit 300 ID Top 2.3 A 250 4.0 A Bottom 5.6 A 200 150 100 , Single Pulse Energy (mJ) 50 ASE V = 25 V DD 0 25 50 75 100 125 150 175 91015_12c Starting TJ, Junction Temperature (°C) Fig. 12c - Maximum Avalanche Energy vs. Drain Current S21-0819-Rev. D, 02-Aug-2021 5 Document Number: 91015 For technical questions, contact: hvm@vishay.com THIS DOCUMENT IS SUBJECT TO CHANGE WITHOUT NOTICE. THE PRODUCTS DESCRIBED HEREIN AND THIS DOCUMENT ARE SUBJECT TO SPECIFIC DISCLAIMERS, SET FORTH AT www.vishay.com/doc?91000