MC33201, MC33202, MC33204, NCV33201, NCV33202, NCV33204DETAILED OPERATING DESCRIPTIONGeneral InformationCircuit Information The MC33201/2/4 family of operational amplifiers are Rail−to−rail performance is achieved at the input of the unique in their ability to swing rail−to−rail on both the input amplifiers by using parallel NPN−PNP differential input and the output with a completely bipolar design. This offers stages. When the inputs are within 800 mV of the negative low noise, high output current capability and a wide rail, the PNP stage is on. When the inputs are more than 800 common mode input voltage range even with low supply mV greater than VEE, the NPN stage is on. This switching of voltages. Operation is guaranteed over an extended input pairs will cause a reversal of input bias currents (see temperature range and at supply voltages of 2.0 V, 3.3 V and Figure 6). Also, slight differences in offset voltage may be 5.0 V and ground. noted between the NPN and PNP pairs. Cross−coupling Since the common mode input voltage range extends from techniques have been used to keep this change to a minimum. VCC to VEE, it can be operated with either single or split In addition to its rail−to−rail performance, the output stage voltage supplies. The MC33201/2/4 are guaranteed not to is current boosted to provide 80 mA of output current, latch or phase reverse over the entire common mode range, enabling the op amp to drive 600 W loads. Because of this however, the inputs should not be allowed to exceed high output current capability, care should be taken not to maximum ratings. exceed the 150°C maximum junction temperature. VCC = +6.0 V VCC = +6.0 V VEE = -6.0 V VEE = -6.0 V RL = 600 W RL = 600 W CL = 100 pF CL = 100 pF TA = 25°C TA = 25°C TAGE (2.0 mV/DIV) TAGE (50 mV/DIV) VOL VOL , OUTPUT , OUTPUT O O V V t, TIME (5.0 ms/DIV) t, TIME (10 ms/DIV) Figure 26. Noninverting Amplifier Slew RateFigure 27. Small Signal Transient Response VCC = +6.0 V VEE = -6.0 V RL = 600 W CL = 100 pF AV = 1.0 TA = 25°C TAGE (2.0 V/DIV) VOL , OUTPUT OV t, TIME (10 ms/DIV) Figure 28. Large Signal Transient Response Surface mount board layout is a critical portion of the total between the board and the package. With the correct pad design. The footprint for the semiconductor packages must be geometry, the packages will self−align when subjected to a the correct size to ensure proper solder connection interface solder reflow process. www.onsemi.com9