Datasheet SPSB081 (STMicroelectronics) - 8

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SPSB081 Maximum ratings 2 Maximum ratings 2.1 Operating range
Within the operating range, the part operates as specified and without parameter deviations. The device may not operate properly if the maximum operating conditions are exceeded. Once taken beyond the operative ratings and returned back within, the part recovers with no damage or degradation. Additional supply voltage and temperature conditions are given separately at the beginning of each electrical specification table. All the voltages are related to the potential at substrate ground.
2.1.1 Supply voltage ranges
All SPI communication, logic, and oscillator parameters work down to VSREG = 3.5 V and are specified accordingly. • SPI thresholds • Oscillator frequency (delay times correctly elapsed) • Internal register status correctly kept (reset at default values for VS < VPOR) • Reset threshold correctly detected
2.2 Absolute maximum ratings
Maximum ratings are absolute ratings; exceeding any one of these values may cause permanent damage to the integrated circuit. All voltages are related to the potential at substrate ground.
Table 2. Absolute maximum ratings Symbol Parameter Condition Min Typ Max Unit
Jump start -0.3 - 28 V VS DC supply voltage Single pulse/tmax < 400 -0.3 - 40 V ms “transient load dump” Jump start -0.3 - 28 V VSREG DC supply voltage Single pulse/tmax < 400 -0.3 - 40 V ms “transient load dump” V1 Stabilized supply voltage, logic supply V1 < VSREG -0.3 - 6.5 V V2 Stabilized supply voltage(1) - -0.3 - 28 V VDI Logic input - -0.3 - V1 + 0.3 V VCLK Logic input - -0.3 - V1 + 0.3 V VCSN Logic input - -0.3 - V1 + 0.3 V VDO Logic output - -0.3 - V1 + 0.3 V VRXDL Logic output - -0.3 - V1 + 0.3 V VRXDC Logic output - -0.3 - V1 + 0.3 V VNRESET Logic output - -0.3 - V1 + 0.3 V VCM Output voltage range - -0.3 - V1 + 0.3 V
DS14048
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Rev 3 page 8/137
Document Outline Device summary Features Applications Description 1 Block diagram and pin description 1.1 Block diagram 1.2 Pin description 2 Maximum ratings 2.1 Operating range 2.1.1 Supply voltage ranges 2.2 Absolute maximum ratings 2.3 Temperature ranges and thermal data 3 Functional description 3.1 Supply VS and VSREG 3.2 Voltage regulators 3.2.1 Voltage regulator: V1 3.2.2 Voltage regulator: V2 3.2.3 Voltage regulator failure 3.2.4 Short to ground detection 3.2.5 Voltage regulator behavior 3.3 Operating modes 3.3.1 Active mode 3.3.2 SW-debug mode 3.3.3 V1_standby mode 3.3.4 Interrupt 3.3.5 VBAT_standby mode 3.4 Wake-up from standby modes 3.4.1 Wake-up inputs 3.5 Functional overview (truth table) 3.6 Configurable window watchdog 3.6.1 Change watchdog timing 3.7 Fail safe mode 3.7.1 Temporary failures 3.7.2 Non recoverable failures - Forced in VBAT_standby mode 3.8 Reset output (NRESET) 3.9 DIAGN output 3.10 V1 overvoltage detection 3.11 LIN bus interfaces (only for SPSB0815 and SPSB0813) 3.11.1 Features 3.11.2 Error handling 3.11.2.1 Dominant TXD_L time out 3.11.2.2 Permanent recessive 3.11.2.3 Permanent dominant 3.11.3 Wake-up from standby modes 3.11.3.1 Pattern wake-up (default) 3.11.3.2 Status change wake-up - Recessive-to-dominant 3.11.3.3 Status change wake-up - Dominant-to-recessive 3.12 CAN FD bus transceiver 3.12.1 Features 3.12.2 CAN transceiver supply 3.12.3 CAN transceiver operating modes 3.12.4 CAN error handling 3.12.4.1 Dominant TXDC time out 3.12.4.2 CAN bus permanent recessive 3.12.4.3 CAN Permanent dominant 3.12.4.4 RXDC permanent recessive 3.12.5 Wake-up by CAN 3.12.6 CAN receive only mode 3.12.7 CAN looping mode 3.13 Power supply fail 3.13.1 VS supply failure 3.13.2 VSREG supply failure 3.14 Thermal state machine 3.15 Power outputs OUT1..4 3.16 Open-load detection 3.17 Overcurrent detection 3.18 Current monitor 3.19 Constant current mode 3.20 Temperature warning and shutdown 3.21 Thermal clusters 3.22 Functional safety management 4 Serial peripheral interface (SPI) 4.1 ST-SPI 4.1.1 Physical layer 4.2 Signal description 4.2.1 Clock and data characteristics 4.2.2 Communication protocol 4.2.2.1 SDI frame 4.2.2.2 Operating code 4.2.2.3 Advanced operation codes 4.2.2.4 Data-in payload 4.2.2.5 SDO frame 4.2.2.6 Global status byte (GSB) 4.2.2.7 Data-out payload 4.3 Address definition 4.3.1 Information registers 4.3.1.1 Device identification registers 4.3.1.2 SPI modes 4.3.1.3 SPI burst read 4.3.1.4 SPI data length 4.3.2 Device application registers (RAM) 4.4 Protocol failure detection 4.4.1 Clock monitor 4.4.2 SCK polarity (CPOL) check 4.4.3 SCK phase (CPHA) check 4.4.4 CSN timeout 4.4.5 SDI stuck at GND 4.4.6 SDI stuck at HIGH 4.4.7 SDO stuck at GND and HIGH 5 Electrical characteristics 5.1 Oscillator 5.2 Power-on reset (VSREG) 5.3 Voltage regulator V1 5.4 Voltage regulator V2 5.5 Reset output 5.6 DIAGN output 5.7 Watchdog 5.8 Current monitor output (CM) 5.9 Outputs OUT1..OUT4 5.10 Power outputs switching times 5.11 Output current threshold 5.12 Wake-up inputs (WU1, DIR/WU2) 5.13 CAN FD transceiver 5.14 LIN transceiver (only for SPSB0815 and SPSB0813) 5.15 SPI 5.16 Debug input 5.17 Interrupt output 5.18 Timer1 and Timer2 5.19 SGND loss comparator 6 Application 7 SPI registers 7.1 Global status byte (GSB) 7.2 Control registers overview 7.3 Status register overview 7.4 Control registers 7.5 Status registers 8 Package information 8.1 QFN32L Epad (5.0x5.0x1.0 mm) package information Revision history