Datasheet SiC931 (Vishay) - 8
| 制造商 | Vishay |
| 描述 | 4.5 V to 18 V Input, 20 A MicroBRICK DC/DC Regulator Module |
| 页数 / 页 | 22 / 8 — SiC931. Sequencing of Input / Output Supplies. Power Good. Enable. … |
| 文件格式/大小 | PDF / 3.6 Mb |
| 文件语言 | 英语 |
SiC931. Sequencing of Input / Output Supplies. Power Good. Enable. Pre-Bias Start-Up. Fig. 10 - PGOOD Window Diagram
该数据表的模型线
文件文字版本
SiC931
www.vishay.com Vishay Siliconix
Sequencing of Input / Output Supplies Power Good
SiC931 has no sequencing requirements on its supplies or SiC931’s power good is an open-drain output. Pull PGOOD enables (VIN, VDD, VDRV, EN). pin high through a > 10 k resistor to use this signal. Power good window is shown in the below diagram. If voltage on
Enable
FB pin is out of this window, PGOOD signal is de-asserted by The SiC931 has an enable pin to turn the part on and off. pulling down to AGND. To prevent false triggering during Driving the pin high enables the device, while driving the pin transient events, PGOOD has a 25 μs blanking time. low disables the device. The EN pin is internally pulled to AGND by a 5 M resistor to prevent unwanted turn on due to a floating GPIO. VFB_Rising_Vth_OV
Pre-Bias Start-Up
(typ. = 0.72 V) VFB_Falling_Vth_OV In case of pre-bias startup, output is monitored through FB (typ. = 0.68 V) V (0.6 V) ref pin. If the sensed voltage on FB is higher than the internal VFB_Falling_Vth_UV reference ramp value, control logic prevents high side and V (typ. = 0.54 V) VFB_Rising_Vth_UV FB (typ. = 0.58 V) low side MOSFETs from switching to avoid negative output voltage spike and excessive current sinking through low side MOSFET. Pull-high PG Pull-low V , 2 V/div OUT
Fig. 10 - PGOOD Window Diagram
V , 2 V/div EN V , 20 V/div SW
Fig. 9 - Pre-Bias Start-Up
S23-0880-Rev. G, 23-Oct-2023
8
Document Number: 79602 For technical questions, contact: powerictechsupport@vishay.com THIS DOCUMENT IS SUBJECT TO CHANGE WITHOUT NOTICE. THE PRODUCTS DESCRIBED HEREIN AND THIS DOCUMENT ARE SUBJECT TO SPECIFIC DISCLAIMERS, SET FORTH AT www.vishay.com/doc?91000
www.vishay.com Vishay Siliconix
Sequencing of Input / Output Supplies Power Good
SiC931 has no sequencing requirements on its supplies or SiC931’s power good is an open-drain output. Pull PGOOD enables (VIN, VDD, VDRV, EN). pin high through a > 10 k resistor to use this signal. Power good window is shown in the below diagram. If voltage on
Enable
FB pin is out of this window, PGOOD signal is de-asserted by The SiC931 has an enable pin to turn the part on and off. pulling down to AGND. To prevent false triggering during Driving the pin high enables the device, while driving the pin transient events, PGOOD has a 25 μs blanking time. low disables the device. The EN pin is internally pulled to AGND by a 5 M resistor to prevent unwanted turn on due to a floating GPIO. VFB_Rising_Vth_OV
Pre-Bias Start-Up
(typ. = 0.72 V) VFB_Falling_Vth_OV In case of pre-bias startup, output is monitored through FB (typ. = 0.68 V) V (0.6 V) ref pin. If the sensed voltage on FB is higher than the internal VFB_Falling_Vth_UV reference ramp value, control logic prevents high side and V (typ. = 0.54 V) VFB_Rising_Vth_UV FB (typ. = 0.58 V) low side MOSFETs from switching to avoid negative output voltage spike and excessive current sinking through low side MOSFET. Pull-high PG Pull-low V , 2 V/div OUT
Fig. 10 - PGOOD Window Diagram
V , 2 V/div EN V , 20 V/div SW
Fig. 9 - Pre-Bias Start-Up
S23-0880-Rev. G, 23-Oct-2023
8
Document Number: 79602 For technical questions, contact: powerictechsupport@vishay.com THIS DOCUMENT IS SUBJECT TO CHANGE WITHOUT NOTICE. THE PRODUCTS DESCRIBED HEREIN AND THIS DOCUMENT ARE SUBJECT TO SPECIFIC DISCLAIMERS, SET FORTH AT www.vishay.com/doc?91000