Datasheet ADP1621 (Analog Devices) - 5

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Data Sheet ADP1621 Parameter Symbol Test Conditions/Comments Min Typ Max Unit
GATE DRIVER GATE Rise Time9 tR CGATE = 3.3 nF 17 ns GATE Fall Time9 tF CGATE = 3.3 nF 13 ns 1 The maximum input voltage is the shunt regulation voltage, which is typically 5.5 V and can range from 5.3 V to 6.0 V over the specified temperature range. 2 The ADP1621 is tested in a feedback servo loop, which servos VFB to the internal reference voltage. The voltage change in FB is measured while VIN is changed from 2.9 V to 5 V. The line regulation is calculated by (∆VFB/VFB) × 100%/∆VIN. 3 The ADP1621 is tested in a feedback servo loop, which servos VFB to the internal reference voltage, and VCOMP is forced from 1.4 V to 1.5 V. The VCOMP range is (1.0 V ≤ VCOMP ≤ 2.0 V). 4 The peak slope-compensation current at the CS pin is typically 70 µA, and effectively clamped at 116 mV. Thus, RS should not exceed 1.6 kΩ (116 mV/70 µA). 5 Guaranteed by design for thermal shutdown. When the thermal junction temperature of the ADP1621 reaches approximately 150°C, the ADP1621 goes into thermal shutdown and the GATE voltage is pulled low. When the junction temperature drops below about 140°C, the soft start sequence is initiated and the ADP1621 resumes normal operation. 6 fOSC is the natural oscil ation frequency, fSYNC is the synchronization frequency, and fSW is the switching frequency. If synchronization is used, then fSW = fSYNC; otherwise, fSW = fOSC. 7 Guaranteed by design and bench characterization. 8 To ensure proper synchronization operation, set the synchronization frequency, fSYNC, to 1.2× of the free-running frequency, fOSC. Although the switching frequency can be synchronized to as high as 1.8 MHz, the peak slope-compensation current decreases at higher synchronization frequencies. It is recommended that the maximum fSYNC be less than 1.4× of fOSC and should not exceed 1.8 MHz. Choose the slope-compensation resistor, RS, for the synchronization frequency (see the Slope Compensation section in the Application Information: Boost Converter section). 9 GATE rise and fall times are measured from 10% to 90% levels. Rev. D | Page 5 of 32 Document Outline FEATURES APPLICATIONS GENERAL DESCRIPTION TYPICAL APPLICATION CIRCUIT TABLE OF CONTENTS REVISION HISTORY SIMPLIFIED BLOCK DIAGRAM SPECIFICATIONS ABSOLUTE MAXIMUM RATINGS THERMAL RESISTANCE ESD CAUTION PIN CONFIGURATION AND FUNCTION DESCRIPTIONS TYPICAL PERFORMANCE CHARACTERISTICS THEORY OF OPERATION CONTROL LOOP CURRENT-SENSE CONFIGURATIONS CURRENT LIMIT UNDERVOLTAGE LOCKOUT SHUTDOWN SOFT START INTERNAL SHUNT REGULATORS SETTING THE OSCILLATOR FREQUENCY AND SYNCHRONIZATION FREQUENCY APPLICATION INFORMATION: BOOST CONVERTER ADIsimPower DESIGN TOOL DUTY CYCLE SETTING THE OUTPUT VOLTAGE INDUCTOR CURRENT RIPPLE INDUCTOR SELECTION INPUT CAPACITOR SELECTION OUTPUT CAPACITOR SELECTION DIODE SELECTION MOSFET SELECTION LOOP COMPENSATION SLOPE COMPENSATION CURRENT LIMIT LIGHT LOAD OPERATION Discontinuous Conduction Mode Pulse-Skipping Modulation RECOMMENDED COMPONENT MANUFACTURERS LAYOUT CONSIDERATIONS EFFICIENCY CONSIDERATIONS EXAMPLES OF APPLICATION CIRCUITS STANDARD BOOST CONVERTER—DESIGN EXAMPLE BOOTSTRAPPED BOOST CONVERTER Low Input and High Output Boost Converter High Input Voltage Boost Converter Circuit SEPIC CONVERTER CIRCUIT LOW VOLTAGE POWER-INPUT CIRCUIT LED DRIVER APPLICATION CIRCUITS RELATED DEVICES OUTLINE DIMENSIONS ORDERING GUIDE