Datasheet L99H92 (STMicroelectronics) - 8

L99H92 Thermal warning and thermal shutdown (TW/TSD) 2.4 Thermal warning and thermal shutdown (TW/TSD)
When the device junction temperature rises above the TjTW_ON threshold for a time longer than tfTjTW/TSD, then the temperature warning flag TW is set and no action is taken. The TW flag can be cleared by an SPI “Read & Clear” command only if the thermal warning condition is no longer present, namely if Tj< TjTW_OFF for a time longer than the corresponding filtering time tfTjTW/TSD. When the junction temperature rises above the TjSD_ON threshold for a time longer than tfTjTW/TSD, then the thermal shutdown flag TSD is set and the external MOSFETs, together with the charge pump are switched-off to protect the device. In particular, the LS MOSFETs gate drivers are forced in sink switch mode to switch off actively the LS MOSFETs with the maximum available current, regardless of the programmed gate discharge current (SLEWDx control bits). The HS MOSFETs gate drivers are forced in sink switch mode for 32µs (up to 64 µs) and as long as VCP>VDH+3 V to switch off actively the HS MOSFETs with the maximum available current, regardless of the programmed gate discharge current. Once the 32 µs (up to 64 µs) are over or VCP<VDH+3 V the HS MOSFETs gate drivers are disabled leaving just an internal resistive connection between gate and source of the HS MOSFETs. The LS gate drivers remain in sink switch mode and the HS gate drivers remain disabled together with the charge pump until the TSD flag is cleared. The TSD flag can be cleared by an SPI “Read & Clear” command only if the thermal shutdown condition is no longer present, namely if Tj< TjSD_OFF for a time longer than the corresponding filtering time tfTjTW/TSD.
2.5 Charge pump (CPOUT)
The dual stage charge pump uses two external flying capacitors, which are switched at the frequency fCP, and one output capacitor connected between the CPOUT pin and the VDH pin. The output of the charge pump has a current limitation (ICP_lim). The NRDY status bit indicates that the charge pump is still not ready to provide enough driving voltage to the gate drivers. This status bit is set during any charge pump startup event because of the device transition from standby mode to active mode or because of the charge pump being enabled once the fault condition/flag that disabled the charge pump is no longer present/set. While the NRDY status bit is set the gate drivers are disabled. The NRDY status bit is automatically cleared once the charge pump output voltage is no longer below the low voltage threshold (VCP_low) for a time longer than the tCP filtering time. Out of standby mode and without any fault the charge pump is enabled. In standby mode, after a thermal shutdown event detection, or in VDH overvoltage condition the charge pump is disabled. To enable the charge pump disabled by a thermal shut down event detection, the TSD flag has to be cleared. To enable the charge pump disabled by VDH overvoltage condition, it is enough that the VDH falls back below the overvoltage threshold (VDHOVT1 or VDHOVT2) for a time longer than the tovuv_filt filtering time. After the charge pump startup, once the NRDY status bit is cleared, if the charge pump output voltage falls below the charge pump output voltage low threshold VCP_low for a time longer than tCP, then the CPLOW flag is set and the external MOSFETs are switched off. In particular, the LS MOSFETs gate drivers are forced in sink switch mode to switch off actively the LS MOSFETs with the maximum available current, regardless of the programmed gate discharge current (SLEWDx control bits). The HS MOSFETs gate drivers are forced in sink switch mode as long as VCP>VDH+3 V, otherwise the HS MOSFETs gate drivers will be disabled and the HS MOSFETs will be switched off passively through the internal resistive connection between gate and source (RGSHx). If the CP_LOW_CONFIG control bit is set to one, the CPLOW status flag becomes a status bit (set and reset automatically) and the gate drivers come out of forced sink switch mode automatically upon recovery from the charge pump low voltage condition. In this case, the status bit is automatically cleared as soon as the charge pump output voltage is no longer below the low voltage threshold for a time longer than tCP. If the CP_LOW_CONFIG control bit is set to zero, the gate drivers come out of forced sink switch mode only once the charge pump low voltage flag CPLOW is cleared via SPI. The charge pump low voltage flag CPLOW can be cleared by an SPI “Read & Clear” command only if the charge pump low voltage condition is no longer present, namely if VCP>VCP_LOW for a time longer than tCP. To reduce electromagnetic emissions, the charge pump frequency dithering is enabled by default. However, the dithering can be disabled through the control bit CPFDD.
DS14069
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Rev 4 page 8/77
Document Outline L99H92 Features Applications Description 1 Block diagram and pins description 1.1 Block diagram 1.2 Pinout 1.3 Pins description 2 Device description 2.1 Supply pins 2.1.1 VS overvoltage warning (VSOVW) 2.1.2 VDH overvoltage (VDHOV) 2.1.3 VDH undervoltage (VDHUV) 2.1.4 VDD overvoltage (VDDOV) 2.1.5 Digital input/output overvoltage (DIOOV) 2.1.6 Power-on reset (POR) 2.2 Standby mode (EN) 2.3 Active mode (OUTE) 2.4 Thermal warning and thermal shutdown (TW/TSD) 2.5 Charge pump (CPOUT) 2.6 Gate drivers 2.6.1 Outputs driving signals (PWM/IN1 and DIR/IN2) 2.6.2 Slew rate control (SLEW) 2.6.3 Short circuit detection / drain-source monitoring (DSHS/DSLS) 2.6.4 Programmable cross current protection time (DT) 2.7 Diagnostic in off-mode (O1DS/O2DS) 2.8 Fail-safe output switch-off input not pin (FSINB) 2.9 Diagnostic not output (DIAGN) 2.10 Current monitors 2.11 Window watchdog (WDG) 3 Application 4 Serial peripheral interface (SPI) 4.1 ST SPI 4.1 4.1.1 Physical layer 4.1.2 Clock and data characteristics 4.1.3 Communication protocol 4.1.4 Address definition 5 Electrical characteristics 5.1 Absolute maximum ratings 5.2 ESD protection 5.3 Thermal data 5.4 Electrical characteristics 5.4.1 Supply, supply monitoring 5.4.2 Power-on reset 5.5 Charge pump 5.6 Full-bridge driver 5.7 VDS monitoring thresholds 5.7.1 Open-load monitoring external full-bridges 5.8 Current sense amplifiers (CSA) 5.9 Fail-safe switch-off input FSINB 5.10 Enable 5.11 DIAGN 5.12 Watchdog 5.13 SPI electrical characteristics 5.14 Oscillator 5.15 Operating modes 6 SPI registers 6.1 Global status byte GSB 6.2 Register map overview 6.3 Status registers 6.4 Control registers 7 Package information 7.1 QFN32L 5x5 mm package information 7.2 TQFP32L 7x7 mm package information Revision history