Datasheet TLV9101, TLV9102, TLV9104 (Texas Instruments) - 9
| 制造商 | Texas Instruments |
| 描述 | 16-V, 1-MHz, Rail-to-Rail Input/Output, Low Power Op Amp |
| 页数 / 页 | 84 / 9 — TLV9101,. TLV9102, TL. V9104. www.ti.com. Figure 5-11. TLV9104S RTE … |
| 文件格式/大小 | PDF / 6.9 Mb |
| 文件语言 | 英语 |
TLV9101,. TLV9102, TL. V9104. www.ti.com. Figure 5-11. TLV9104S RTE Package(A). 16-Pin WQFN With Exposed Thermal Pad. Top View
该数据表的模型线
文件文字版本
link to page 30 link to page 30 link to page 30
TLV9101, TLV9102, TL V9104 www.ti.com
SBOS943E – FEBRUARY 2019 – REVISED AUGUST 2021 IN1– OUT1 OUT4 IN4– 16 15 14 13 IN1+ 1 12 IN4+ V+ 2 11 V– Thermal IN2+ 3 Pad 10 IN3+ IN2– 4 9 IN3– 5 6 7 8 Not to scale OUT2 OUT3 SHDN12 SHDN34 A. Connect thermal pad to V–. See Section 7.3.9 for more information.
Figure 5-11. TLV9104S RTE Package(A) 16-Pin WQFN With Exposed Thermal Pad Top View Table 5-6. Pin Functions: TLV9104S PIN I/O DESCRIPTION NAME NO.
IN1+ 1 I Noninverting input, channel 1 IN1– 16 I Inverting input, channel 1 IN2+ 3 I Noninverting input, channel 2 IN2– 4 I Inverting input, channel 2 IN3+ 10 I Noninverting input, channel 3 IN3– 9 I Inverting input, channel 3 IN4+ 12 I Noninverting input, channel 4 IN4– 13 I Inverting input, channel 4 OUT1 15 O Output, channel 1 OUT2 5 O Output, channel 2 OUT3 8 O Output, channel 3 OUT4 14 O Output, channel 4 Shutdown, channels 1 and 2: low = amplifiers enabled, high = amplifiers SHDN12 6 I disabled. See Section 7.3.10 for more information. Shutdown, channels 3 and 4: low = amplifiers enabled, high = amplifiers SHDN34 7 I disabled. See Section 7.3.10 for more information. V+ 2 — Positive (highest) power supply V– 11 — Negative (lowest) power supply Copyright © 2021 Texas Instruments Incorporated Submit Document Feedback 9 Product Folder Links: TLV9101 TLV9102 TLV9104 Document Outline 1 Features 2 Applications 3 Description Table of Contents 4 Revision History 5 Pin Configuration and Functions 6 Specifications 6.1 Absolute Maximum Ratings 6.2 ESD Ratings 6.3 Recommended Operating Conditions 6.4 Thermal Information for Single Channel 6.5 Thermal Information for Dual Channel 6.6 Thermal Information for Quad Channel 6.7 Electrical Characteristics 6.8 Typical Characteristics 7 Detailed Description 7.1 Overview 7.2 Functional Block Diagram 7.3 Feature Description 7.3.1 EMI Rejection 7.3.2 Phase Reversal Protection 7.3.3 Thermal Protection 7.3.4 Capacitive Load and Stability 7.3.5 Common-Mode Voltage Range 7.3.6 Electrical Overstress 7.3.7 Overload Recovery 7.3.8 Typical Specifications and Distributions 7.3.9 Packages With an Exposed Thermal Pad 7.3.10 Shutdown 7.4 Device Functional Modes 8 Application and Implementation 8.1 Application Information 8.2 Typical Applications 8.2.1 High Voltage Precision Comparator 8.2.1.1 Design Requirements 8.2.1.2 Detailed Design Procedure 8.2.1.3 Application Curve 9 Power Supply Recommendations 10 Layout 10.1 Layout Guidelines 10.2 Layout Example 11 Device and Documentation Support 11.1 Device Support 11.1.1 Development Support 11.1.1.1 TINA-TI™ (Free Software Download) 11.2 Documentation Support 11.2.1 Related Documentation 11.3 Receiving Notification of Documentation Updates 11.4 Support Resources 11.5 Trademarks 11.6 Electrostatic Discharge Caution 11.7 Glossary 12 Mechanical, Packaging, and Orderable Information
TLV9101, TLV9102, TL V9104 www.ti.com
SBOS943E – FEBRUARY 2019 – REVISED AUGUST 2021 IN1– OUT1 OUT4 IN4– 16 15 14 13 IN1+ 1 12 IN4+ V+ 2 11 V– Thermal IN2+ 3 Pad 10 IN3+ IN2– 4 9 IN3– 5 6 7 8 Not to scale OUT2 OUT3 SHDN12 SHDN34 A. Connect thermal pad to V–. See Section 7.3.9 for more information.
Figure 5-11. TLV9104S RTE Package(A) 16-Pin WQFN With Exposed Thermal Pad Top View Table 5-6. Pin Functions: TLV9104S PIN I/O DESCRIPTION NAME NO.
IN1+ 1 I Noninverting input, channel 1 IN1– 16 I Inverting input, channel 1 IN2+ 3 I Noninverting input, channel 2 IN2– 4 I Inverting input, channel 2 IN3+ 10 I Noninverting input, channel 3 IN3– 9 I Inverting input, channel 3 IN4+ 12 I Noninverting input, channel 4 IN4– 13 I Inverting input, channel 4 OUT1 15 O Output, channel 1 OUT2 5 O Output, channel 2 OUT3 8 O Output, channel 3 OUT4 14 O Output, channel 4 Shutdown, channels 1 and 2: low = amplifiers enabled, high = amplifiers SHDN12 6 I disabled. See Section 7.3.10 for more information. Shutdown, channels 3 and 4: low = amplifiers enabled, high = amplifiers SHDN34 7 I disabled. See Section 7.3.10 for more information. V+ 2 — Positive (highest) power supply V– 11 — Negative (lowest) power supply Copyright © 2021 Texas Instruments Incorporated Submit Document Feedback 9 Product Folder Links: TLV9101 TLV9102 TLV9104 Document Outline 1 Features 2 Applications 3 Description Table of Contents 4 Revision History 5 Pin Configuration and Functions 6 Specifications 6.1 Absolute Maximum Ratings 6.2 ESD Ratings 6.3 Recommended Operating Conditions 6.4 Thermal Information for Single Channel 6.5 Thermal Information for Dual Channel 6.6 Thermal Information for Quad Channel 6.7 Electrical Characteristics 6.8 Typical Characteristics 7 Detailed Description 7.1 Overview 7.2 Functional Block Diagram 7.3 Feature Description 7.3.1 EMI Rejection 7.3.2 Phase Reversal Protection 7.3.3 Thermal Protection 7.3.4 Capacitive Load and Stability 7.3.5 Common-Mode Voltage Range 7.3.6 Electrical Overstress 7.3.7 Overload Recovery 7.3.8 Typical Specifications and Distributions 7.3.9 Packages With an Exposed Thermal Pad 7.3.10 Shutdown 7.4 Device Functional Modes 8 Application and Implementation 8.1 Application Information 8.2 Typical Applications 8.2.1 High Voltage Precision Comparator 8.2.1.1 Design Requirements 8.2.1.2 Detailed Design Procedure 8.2.1.3 Application Curve 9 Power Supply Recommendations 10 Layout 10.1 Layout Guidelines 10.2 Layout Example 11 Device and Documentation Support 11.1 Device Support 11.1.1 Development Support 11.1.1.1 TINA-TI™ (Free Software Download) 11.2 Documentation Support 11.2.1 Related Documentation 11.3 Receiving Notification of Documentation Updates 11.4 Support Resources 11.5 Trademarks 11.6 Electrostatic Discharge Caution 11.7 Glossary 12 Mechanical, Packaging, and Orderable Information