Datasheet MAX3280E, MAX3281E, MAX3283E, MAX3284E (Analog Devices) - 6

MAX3280E/MAX3281E/ ±15kV ESD-Protected 52Mbps, 3V to 5.5V, MAX3283E/MAX3284E SOT23 RS-485/RS-422 True Fail-Safe Receivers
Pin Description PIN NAME FUNCTION MAX3280E MAX3281E MAX3283E MAX3284E
Positive Supply: 3V ≤ V 1 1 1 1 V CC ≤ 5.5V. Bypass with a 0.1µF CC capacitor to GND. 2 2 2 2 GND Ground Receiver Output. RO will be high if (V 3 3 3 3 RO A - VB) ≥ -50mV. RO will be low if (VA - VB) ≤ -200mV. 4 4 4 4 B Inverting Receiver Input — — 5 — Receiver Output Enable. Drive EN low to enable RO. When EN EN is high, RO is high impedance. Receiver Output Enable. Drive EN high to enable RO. When — 5 — — EN EN is low, RO is high impedance. Low-Voltage Logic-Level Supply Voltage. VL is a user-defined — — — 5 VL voltage, ranging from 1.65V to VCC. RO output high is pulled up to VL. Bypass with a 0.1µF capacitor to GND. 5 6 6 6 A Noninverting Receiver Input
Detailed Description
±15kV ESD without damage. After an ESD event, this The MAX3280E/MAX3281E/MAX3283E/MAX3284E are family of parts continues working without latchup. single, true fail-safe receivers designed to operate at data ESD protection can be tested in several ways. The rates up to 52Mbps. The fail-safe architecture guarantees receiver inputs are characterized for protection to the a high output signal if both input terminals are open or following: shorted together. See the True Fail-Safe section. This ● ±15kV using the Human Body Model feature assures a stable and predictable output logic state with any transmitter driving the line. These receivers func- ● ±6kV using the Contact Discharge method specified tion with a 3.3V or 5V supply voltage and feature excellent in IEC 1000-4-2 (formerly IEC 801-2) propagation delay times (15ns). ● ±12kV using the Air-Gap Discharge method specified The MAX3280E is a single receiver available in a 5-pin in IEC 1000-4-2 (formerly IEC 801-2) SOT23 package. The MAX3281E (EN, active high) and
ESD Test Conditions
MAX3283E (EN, active low) are single receivers that also contain an enable pin. Both the MAX3281E and ESD performance depends on a number of conditions. MAX3283E are available in a 6-pin SOT23 package. The Contact Maxim for a reliability report that documents test MAX3284E is a single receiver that contains a V setup, methodology, and results. L pin, which allows communication with low-level logic included
Human Body Model
in digital FPGAs. The MAX3284E is available in a 6-pin Figure 3a shows the Human Body Model, and Figure SOT23 package. 3b shows the current waveform it generates when dis- The MAX3284E’s low-level logic application allows users charged into a low impedance. This model consists of a to set the logic levels. A logic high level of 1.65V will limit 100pF capacitor charged to the ESD voltage of interest, the maximum data rate to 20Mbps. which is then discharged into the device through a 1.5kW ±
15kV ESD Protection
resistor. ESD-protection structures are incorporated on the
IEC 1000-4-2
receiver input pins to protect against ESD encountered Since January 1996, all equipment manufactured during handling and assembly. The MAX3280E/ and/or sold in the European community has been MAX3281E/MAX3283E/MAX3284E receiver inputs (A, required to meet the stringent IEC 1000-4-2 specifica- B) have extra protection against static electricity found tion. The IEC 1000-4-2 standard covers ESD test- in normal operation. Maxim’s engineers developed ing and performance of finished equipment; it does state-of-the-art structures to protect these pins against not specifically refer to integrated circuits. The MAX3280E/MAX3281E/MAX3283E/MAX3284E help www.maximintegrated.com Maxim Integrated │ 6