Datasheet MAX3280E, MAX3281E, MAX3283E, MAX3284E (Analog Devices) - 8

MAX3280E/MAX3281E/ ±15kV ESD-Protected 52Mbps, 3V to 5.5V, MAX3283E/MAX3284E SOT23 RS-485/RS-422 True Fail-Safe Receivers provide the same clock to their respective circuits. (48kW), which allows up to 128 receivers on the bus. Thus, minimal package-to-package skew is critical. The Any combination of these RS-485 receivers with a total skew must be kept well below the period of the clock of 32 unit loads can be connected to the same bus. signal to ensure that all of the circuits on the network are synchronized.
Thermal Protection
The MAX3280E/MAX3281E/MAX3283E/MAX3284E fea-
128 Receivers on the Bus
ture thermal protection. Thermal protection sets the out- The standard RS-485 input impedance is 12kW (one- put stage in high-impedance mode when a short circuit unit load). The standard RS-485 transmitter can drive occurs at the output, limiting both the power dissipation 32 unit loads. The MAX3280E/MAX3281E/MAX3283E/ and temperature. The thermal temperature threshold is MAX3284E present a 1/4-unit-load input impedance +165°C, with a hysteresis of 20°C.
Test Circuits/Timing Diagrams
VOH V RO CC/2 VCC/2 VOL OUTPUT tPHL tPLH 1V A -1V B INPUT fIN = 1MHz tr, tf 3ns Figure 1. Receiver Propagation Delay S3 S1 1.5V 1kΩ VCC -1.5V VID R S2 CL GENERATOR 50Ω VCC VCC S1 OPEN S1 CLOSED VCC/2 S2 CLOSED VCC/2 S2 OPEN S3 = 1.5V S3 = -1.5V EN 0 EN 0 tPRZH tPRZL OUT VOH VCC VCC/2 OUT VCC/2 0 VOL VCC VCC S1 OPEN S1 CLOSED VCC/2 S2 CLOSED VCC/2 S2 OPEN S3 = 1.5V S3 = -1.5V EN 0 EN 0 tPRHZ tPRLZ OUT VOH 0.25V VCC OUT 0 0.25V V FOR MAX3281E THE ENABLE SIGNAL IS INVERTED. OL Figure 2. MAX3281E/MAX3283E Receiver Enable/Disable Timing www.maximintegrated.com Maxim Integrated │ 8