Datasheet TLV9161, TLV9162, TLV9164 (Texas Instruments) - 6
| 制造商 | Texas Instruments |
| 描述 | TLV916x 16V, 11MHz, Rail-to-Rail Input/Output, Low Offset Voltage, Low Noise Op Amp |
| 页数 / 页 | 69 / 6 — TLV9161, TL. V9162,. TLV9164. www.ti.com. Figure 4-7. TLV9164 D and PW … |
| 文件格式/大小 | PDF / 4.7 Mb |
| 文件语言 | 英语 |
TLV9161, TL. V9162,. TLV9164. www.ti.com. Figure 4-7. TLV9164 D and PW Package. 14-Pin SOIC and TSSOP. (Top View)
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TLV9161, TL V9162, TLV9164
SBOSA68D – NOVEMBER 2021 – REVISED MARCH 2024
www.ti.com
OUT1 1 14 OUT4 IN1 2 ± 13 IN4± IN1+ 3 12 IN4+ V+ 4 11 V± IN2+ 5 10 IN3+ IN2 6 ± 9 IN3± OUT2 7 8 OUT3 Not to scale
Figure 4-7. TLV9164 D and PW Package 14-Pin SOIC and TSSOP (Top View) Table 4-5. Pin Functions: TLV9164 PIN I/O DESCRIPTION NAME NO.
IN1+ 3 I Noninverting input, channel 1 IN1– 2 I Inverting input, channel 1 IN2+ 5 I Noninverting input, channel 2 IN2– 6 I Inverting input, channel 2 IN3+ 10 I Noninverting input, channel 3 IN3– 9 I Inverting input, channel 3 IN4+ 12 I Noninverting input, channel 4 IN4– 13 I Inverting input, channel 4 OUT1 1 O Output, channel 1 OUT2 7 O Output, channel 2 OUT3 8 O Output, channel 3 OUT4 14 O Output, channel 4 V+ 4 — Positive (highest) power supply V– 11 — Negative (lowest) power supply 6 Submit Document Feedback Copyright © 2024 Texas Instruments Incorporated Product Folder Links: TLV9161 TLV9162 TLV9164 Document Outline 1 Features 2 Applications 3 Description Table of Contents 4 Pin Configuration and Functions 5 Specifications 5.1 Absolute Maximum Ratings 5.2 ESD Ratings 5.3 Recommended Operating Conditions 5.4 Thermal Information for Single Channel 5.5 Thermal Information for Dual Channel 5.6 Thermal Information for Quad Channel 5.7 Electrical Characteristics 5.8 Typical Characteristics 6 Detailed Description 6.1 Overview 6.2 Functional Block Diagram 6.3 Feature Description 6.3.1 Input Protection Circuitry 6.3.2 EMI Rejection 6.3.3 Thermal Protection 6.3.4 Capacitive Load and Stability 6.3.5 Common-Mode Voltage Range 6.3.6 Phase Reversal Protection 6.3.7 Electrical Overstress 6.3.8 Overload Recovery 6.3.9 Typical Specifications and Distributions 6.3.10 Packages With an Exposed Thermal Pad 6.3.11 Shutdown 6.4 Device Functional Modes 7 Application and Implementation 7.1 Application Information 7.2 Typical Applications 7.2.1 Low-Side Current Measurement 7.2.1.1 Design Requirements 7.2.1.2 Detailed Design Procedure 7.2.1.3 Application Curve 7.2.2 Buffered Multiplexer 7.3 Power Supply Recommendations 7.4 Layout 7.4.1 Layout Guidelines 7.4.2 Layout Example 8 Device and Documentation Support 8.1 Device Support 8.1.1 Development Support 8.1.1.1 TINA-TI™ (Free Software Download) 8.2 Documentation Support 8.2.1 Related Documentation 8.3 Receiving Notification of Documentation Updates 8.4 Support Resources 8.5 Trademarks 8.6 Electrostatic Discharge Caution 8.7 Glossary 9 Revision History 10 Mechanical, Packaging, and Orderable Information
SBOSA68D – NOVEMBER 2021 – REVISED MARCH 2024
www.ti.com
OUT1 1 14 OUT4 IN1 2 ± 13 IN4± IN1+ 3 12 IN4+ V+ 4 11 V± IN2+ 5 10 IN3+ IN2 6 ± 9 IN3± OUT2 7 8 OUT3 Not to scale
Figure 4-7. TLV9164 D and PW Package 14-Pin SOIC and TSSOP (Top View) Table 4-5. Pin Functions: TLV9164 PIN I/O DESCRIPTION NAME NO.
IN1+ 3 I Noninverting input, channel 1 IN1– 2 I Inverting input, channel 1 IN2+ 5 I Noninverting input, channel 2 IN2– 6 I Inverting input, channel 2 IN3+ 10 I Noninverting input, channel 3 IN3– 9 I Inverting input, channel 3 IN4+ 12 I Noninverting input, channel 4 IN4– 13 I Inverting input, channel 4 OUT1 1 O Output, channel 1 OUT2 7 O Output, channel 2 OUT3 8 O Output, channel 3 OUT4 14 O Output, channel 4 V+ 4 — Positive (highest) power supply V– 11 — Negative (lowest) power supply 6 Submit Document Feedback Copyright © 2024 Texas Instruments Incorporated Product Folder Links: TLV9161 TLV9162 TLV9164 Document Outline 1 Features 2 Applications 3 Description Table of Contents 4 Pin Configuration and Functions 5 Specifications 5.1 Absolute Maximum Ratings 5.2 ESD Ratings 5.3 Recommended Operating Conditions 5.4 Thermal Information for Single Channel 5.5 Thermal Information for Dual Channel 5.6 Thermal Information for Quad Channel 5.7 Electrical Characteristics 5.8 Typical Characteristics 6 Detailed Description 6.1 Overview 6.2 Functional Block Diagram 6.3 Feature Description 6.3.1 Input Protection Circuitry 6.3.2 EMI Rejection 6.3.3 Thermal Protection 6.3.4 Capacitive Load and Stability 6.3.5 Common-Mode Voltage Range 6.3.6 Phase Reversal Protection 6.3.7 Electrical Overstress 6.3.8 Overload Recovery 6.3.9 Typical Specifications and Distributions 6.3.10 Packages With an Exposed Thermal Pad 6.3.11 Shutdown 6.4 Device Functional Modes 7 Application and Implementation 7.1 Application Information 7.2 Typical Applications 7.2.1 Low-Side Current Measurement 7.2.1.1 Design Requirements 7.2.1.2 Detailed Design Procedure 7.2.1.3 Application Curve 7.2.2 Buffered Multiplexer 7.3 Power Supply Recommendations 7.4 Layout 7.4.1 Layout Guidelines 7.4.2 Layout Example 8 Device and Documentation Support 8.1 Device Support 8.1.1 Development Support 8.1.1.1 TINA-TI™ (Free Software Download) 8.2 Documentation Support 8.2.1 Related Documentation 8.3 Receiving Notification of Documentation Updates 8.4 Support Resources 8.5 Trademarks 8.6 Electrostatic Discharge Caution 8.7 Glossary 9 Revision History 10 Mechanical, Packaging, and Orderable Information