Datasheet TLV9161, TLV9162, TLV9164 (Texas Instruments) - 9

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TLV9161, TLV9162, TL V9164 www.ti.com
SBOSA68D – NOVEMBER 2021 – REVISED MARCH 2024
5.7 Electrical Characteristics
For VS = (V+) – (V–) = 2.7 V to 16 V (±1.35 V to ±8 V) at TA = 25°C, RL = 10 kΩ connected to VS / 2, VCM = VS / 2, and VOUT = VS / 2, unless otherwise noted.
PARAMETER TEST CONDITIONS MIN TYP MAX UNIT OFFSET VOLTAGE
±0.21 ±1 VOS Input offset voltage VCM = V– mV TA = –40°C to 125°C ±1.2 dVOS/dT Input offset voltage drift VCM = V– TA = –40°C to 125°C ±0.25 µV/℃ TLV9161, TLV9162, V ±0.45 ±2 CM = V–, VS = 5 V to 16 V TA = –40°C to 125°C ±0.45 ±3 TLV9162SIRUGR, V ±0.45 ±2.8 CM = V–, VS = 5 V to 16 V(1) T Input offset voltage versus A = –40°C to 125°C ±0.45 ±3.1 PSRR μV/V power supply TLV9164, V ±0.45 ±2.2 CM = V–, VS = 5 V to 16 V TA = –40°C to 125°C ±0.45 ±3.8 TLV9161, TLV9162, TLV9164, VCM = V–, VS = 2.7 TA = –40°C to 125°C ±2 ±12 V to 16 V(1) DC channel separation 0.4 µV/V
INPUT BIAS CURRENT
IB Input bias current ±10 pA IOS Input offset current ±10 pA
NOISE
2.7 μVPP EN Input voltage noise f = 0.1 Hz to 10 Hz 0.49 µVRMS f = 1 kHz 6.8 eN Input voltage noise density nV/√Hz f = 10 kHz 4.2 iN Input current noise density f = 1 kHz 55 fA/√Hz
INPUT VOLTAGE RANGE
Common-mode voltage VCM (V–) (V+) V range VS = 16 V, V– < VCM < (V+) – 85 110 2 V (PMOS pair) VS = 5 V, V– < VCM < (V+) – 2 V (PMOS pair)(1) 75 98 Common-mode rejection CMRR VS = 2.7 V, V– < VCM < (V+) – T dB ratio A = –40°C to 125°C 90 2 V (PMOS pair) VS = 2.7 – 16 V, (V+) – 1 V < 78 VCM < V+ (NMOS pair) (V+) – 2 V < VCM < (V+) – 1 V See Figure 5-6
INPUT IMPEDANCE
ZID Differential 100 || 9 MΩ || pF ZICM Common-mode 6 || 1 TΩ || pF
OPEN-LOOP GAIN
VS = 16 V, VCM = VS / 2, 120 136 (V–) + 0.1 V < VO < (V+) – 0.1 V TA = –40°C to 125°C 136 VS = 5 V, VCM = VS / 2, 104 125 AOL Open-loop voltage gain (V–) + 0.1 V < VO < (V+) – dB 0.1 V(1) TA = –40°C to 125°C 125 VS = 2.7 V, VCM = VS / 2, 90 105 (V–) + 0.1 V < VO < (V+) – 0.1 V(1) TA = –40°C to 125°C 105
FREQUENCY RESPONSE
GBW Gain-bandwidth product 11 MHz SR Slew rate VS = 16 V, G = +1, VSTEP = 10 V, CL = 20 pF(3) 33 V/μs Copyright © 2024 Texas Instruments Incorporated Submit Document Feedback 9 Product Folder Links: TLV9161 TLV9162 TLV9164 Document Outline 1 Features 2 Applications 3 Description Table of Contents 4 Pin Configuration and Functions 5 Specifications 5.1 Absolute Maximum Ratings 5.2 ESD Ratings 5.3 Recommended Operating Conditions 5.4 Thermal Information for Single Channel 5.5 Thermal Information for Dual Channel 5.6 Thermal Information for Quad Channel 5.7 Electrical Characteristics 5.8 Typical Characteristics 6 Detailed Description 6.1 Overview 6.2 Functional Block Diagram 6.3 Feature Description 6.3.1 Input Protection Circuitry 6.3.2 EMI Rejection 6.3.3 Thermal Protection 6.3.4 Capacitive Load and Stability 6.3.5 Common-Mode Voltage Range 6.3.6 Phase Reversal Protection 6.3.7 Electrical Overstress 6.3.8 Overload Recovery 6.3.9 Typical Specifications and Distributions 6.3.10 Packages With an Exposed Thermal Pad 6.3.11 Shutdown 6.4 Device Functional Modes 7 Application and Implementation 7.1 Application Information 7.2 Typical Applications 7.2.1 Low-Side Current Measurement 7.2.1.1 Design Requirements 7.2.1.2 Detailed Design Procedure 7.2.1.3 Application Curve 7.2.2 Buffered Multiplexer 7.3 Power Supply Recommendations 7.4 Layout 7.4.1 Layout Guidelines 7.4.2 Layout Example 8 Device and Documentation Support 8.1 Device Support 8.1.1 Development Support 8.1.1.1 TINA-TI™ (Free Software Download) 8.2 Documentation Support 8.2.1 Related Documentation 8.3 Receiving Notification of Documentation Updates 8.4 Support Resources 8.5 Trademarks 8.6 Electrostatic Discharge Caution 8.7 Glossary 9 Revision History 10 Mechanical, Packaging, and Orderable Information