filename /C/Users/pradeep.pushparajan/AppData/Local/Adobe/InDesign/Version 11.0/en_US/Caches/InDesign ClipboardScrap1.pdf filename /C/Users/pradeep.pushparajan/AppData/Local/Adobe/InDesign/Version 11.0/en_US/Caches/InDesign ClipboardScrap1.pdf MAX6173–MAX6177 High-Precision Voltage References with Temperature Sensor Absolute Maximum Ratings IN to GND ..-0.3V to +42V Operating Temperature Range ... -40°C to +125°C OUT, TRIM, TEMP to GND ..-0.3V to (VIN + 0.3V) Junction Temperature ..+150°C Output Short-Circuit to GND ... 5s Storage Temperature Range .. -65°C to +150°C Continuous Power Dissipation (TA = +70°C) (Note1) Lead Temperature (soldering, 10s) ...+300°C 8-Pin SO (derate 7.6mW/°C above +70°C) ...606mW Soldering Temperature (reflow) ...+260°C Stresses beyond those listed under “Absolute Maximum Ratings” may cause permanent damage to the device. These are stress ratings only, and functional operation of the device at these or any other conditions beyond those indicated in the operational sections of the specifications is not implied. Exposure to absolute maximum rating conditions for extended periods may affect device reliability. Package Thermal Characteristics (Note 1) 8 SOPACKAGE CODES8+4 Outline Number 21-0041 Land Pattern Number 90-0096Thermal Resistance, Single-Layer Board Junction to Ambient - θJA 170 Junction to Case - θJC 40 Thermal Resistance, Multi-Layer Board Junction to Ambient - θJA 132°C/W Junction to Case - θJC 38°C/W 8 SOPACKAGE CODES8+22 Outline Number 21-0041 Land Pattern Number 90-0096Thermal Resistance, Single-Layer Board Junction to Ambient - θJA 170°C/W Junction to Case - θJC 40°C/W Thermal Resistance, Multi-Layer Board Junction to Ambient - θJA 132°C/W Junction to Case - θJC 38°C/W For the latest package outline information and land patterns (footprints), go to www.maximintegrated.com/packages . Note that a “+”, “#”, or “-” in the package code indicates RoHS status only. Package drawings may show a different suffix character, but the drawing pertains to the package regardless of RoHS status. Package thermal resistances were obtained using the method described in JEDEC specification JESD51-7, using a four-layer board. For detailed information on package thermal considerations, refer to www.maximintegrated.com/thermal-tutorial . www.maximintegrated.com Maxim Integrated │ 2 Document Outline _GoBack