Datasheet TLV9152 (Texas Instruments) - 8
| 制造商 | Texas Instruments |
| 描述 | Dual, 16-v, 4.5-mhz, Low-power Operational Amplifier |
| 页数 / 页 | 82 / 8 — TLV9151, TL. V9152,. TLV9154. www.ti.com. Figure 5-7. TLV9154 D, PW, and … |
| 文件格式/大小 | PDF / 6.5 Mb |
| 文件语言 | 英语 |
TLV9151, TL. V9152,. TLV9154. www.ti.com. Figure 5-7. TLV9154 D, PW, and DYY Packages. 14-Pin SOIC, TSSOP, and SOT-23. (Top View)
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TLV9151, TL V9152, TLV9154
SBOS986E – OCTOBER 2019 – REVISED JANUARY 2022
www.ti.com
1 4 T T U U OUT1 1 14 OUT4 O O IN1 2 ± 13 IN4± IN1 1 ± 12 IN4± IN1+ 3 12 IN4+ 4 3 V+ 4 11 V± 1 1 IN1+ 2 11 IN4+ IN2+ 5 10 IN3+ V+ 3 10 V IN2 6 ± 9 IN3± ± OUT2 7 8 OUT3 IN2+ 4 9 IN3+ 6 7 Not to scale
Figure 5-7. TLV9154 D, PW, and DYY Packages
IN2 5 ± 8 IN3±
14-Pin SOIC, TSSOP, and SOT-23
2 3
(Top View)
T T Not to scale U U O O
Figure 5-8. TLV9154 RUC Package 14-Pin X2QFN (Top View) Table 5-5. Pin Functions: TLV9154 PIN I/O DESCRIPTION NAME SOIC, TSSOP, SOT-23 X2QFN
IN1+ 3 2 I Noninverting input, channel 1 IN1– 2 1 I Inverting input, channel 1 IN2+ 5 4 I Noninverting input, channel 2 IN2– 6 5 I Inverting input, channel 2 IN3+ 10 9 I Noninverting input, channel 3 IN3– 9 8 I Inverting input, channel 3 IN4+ 12 11 I Noninverting input, channel 4 IN4– 13 12 I Inverting input, channel 4 NC — — — Do not connect OUT1 1 14 O Output, channel 1 OUT2 7 6 O Output, channel 2 OUT3 8 7 O Output, channel 3 OUT4 14 13 O Output, channel 4 V+ 4 3 — Positive (highest) power supply V– 11 10 — Negative (lowest) power supply 8 Submit Document Feedback Copyright © 2022 Texas Instruments Incorporated Product Folder Links: TLV9151 TLV9152 TLV9154 Document Outline 1 Features 2 Applications 3 Description Table of Contents 4 Revision History 5 Pin Configuration and Functions 6 Specifications 6.1 Absolute Maximum Ratings 6.2 ESD Ratings 6.3 Recommended Operating Conditions 6.4 Thermal Information for Single Channel 6.5 Thermal Information for Dual Channel 6.6 Thermal Information for Quad Channel 6.7 Electrical Characteristics 6.8 Typical Characteristics 7 Detailed Description 7.1 Overview 7.2 Functional Block Diagram 7.3 Feature Description 7.3.1 EMI Rejection 7.3.2 Thermal Protection 7.3.3 Capacitive Load and Stability 7.3.4 Common-Mode Voltage Range 7.3.5 Phase Reversal Protection 7.3.6 Electrical Overstress 7.3.7 Overload Recovery 7.3.8 Typical Specifications and Distributions 7.3.9 Packages With an Exposed Thermal Pad 7.3.10 Shutdown 7.4 Device Functional Modes 8 Application and Implementation 8.1 Application Information 8.2 Typical Applications 8.2.1 Low-Side Current Measurement 8.2.1.1 Design Requirements 8.2.1.2 Detailed Design Procedure 8.2.1.3 Application Curves 9 Power Supply Recommendations 10 Layout 10.1 Layout Guidelines 10.2 Layout Example 11 Device and Documentation Support 11.1 Device Support 11.1.1 Development Support 11.1.1.1 TINA-TI™ (Free Software Download) 11.1.1.2 TI Precision Designs 11.2 Documentation Support 11.2.1 Related Documentation 11.3 Receiving Notification of Documentation Updates 11.4 Support Resources 11.5 Trademarks 11.6 Electrostatic Discharge Caution 11.7 Glossary 12 Mechanical, Packaging, and Orderable Information
SBOS986E – OCTOBER 2019 – REVISED JANUARY 2022
www.ti.com
1 4 T T U U OUT1 1 14 OUT4 O O IN1 2 ± 13 IN4± IN1 1 ± 12 IN4± IN1+ 3 12 IN4+ 4 3 V+ 4 11 V± 1 1 IN1+ 2 11 IN4+ IN2+ 5 10 IN3+ V+ 3 10 V IN2 6 ± 9 IN3± ± OUT2 7 8 OUT3 IN2+ 4 9 IN3+ 6 7 Not to scale
Figure 5-7. TLV9154 D, PW, and DYY Packages
IN2 5 ± 8 IN3±
14-Pin SOIC, TSSOP, and SOT-23
2 3
(Top View)
T T Not to scale U U O O
Figure 5-8. TLV9154 RUC Package 14-Pin X2QFN (Top View) Table 5-5. Pin Functions: TLV9154 PIN I/O DESCRIPTION NAME SOIC, TSSOP, SOT-23 X2QFN
IN1+ 3 2 I Noninverting input, channel 1 IN1– 2 1 I Inverting input, channel 1 IN2+ 5 4 I Noninverting input, channel 2 IN2– 6 5 I Inverting input, channel 2 IN3+ 10 9 I Noninverting input, channel 3 IN3– 9 8 I Inverting input, channel 3 IN4+ 12 11 I Noninverting input, channel 4 IN4– 13 12 I Inverting input, channel 4 NC — — — Do not connect OUT1 1 14 O Output, channel 1 OUT2 7 6 O Output, channel 2 OUT3 8 7 O Output, channel 3 OUT4 14 13 O Output, channel 4 V+ 4 3 — Positive (highest) power supply V– 11 10 — Negative (lowest) power supply 8 Submit Document Feedback Copyright © 2022 Texas Instruments Incorporated Product Folder Links: TLV9151 TLV9152 TLV9154 Document Outline 1 Features 2 Applications 3 Description Table of Contents 4 Revision History 5 Pin Configuration and Functions 6 Specifications 6.1 Absolute Maximum Ratings 6.2 ESD Ratings 6.3 Recommended Operating Conditions 6.4 Thermal Information for Single Channel 6.5 Thermal Information for Dual Channel 6.6 Thermal Information for Quad Channel 6.7 Electrical Characteristics 6.8 Typical Characteristics 7 Detailed Description 7.1 Overview 7.2 Functional Block Diagram 7.3 Feature Description 7.3.1 EMI Rejection 7.3.2 Thermal Protection 7.3.3 Capacitive Load and Stability 7.3.4 Common-Mode Voltage Range 7.3.5 Phase Reversal Protection 7.3.6 Electrical Overstress 7.3.7 Overload Recovery 7.3.8 Typical Specifications and Distributions 7.3.9 Packages With an Exposed Thermal Pad 7.3.10 Shutdown 7.4 Device Functional Modes 8 Application and Implementation 8.1 Application Information 8.2 Typical Applications 8.2.1 Low-Side Current Measurement 8.2.1.1 Design Requirements 8.2.1.2 Detailed Design Procedure 8.2.1.3 Application Curves 9 Power Supply Recommendations 10 Layout 10.1 Layout Guidelines 10.2 Layout Example 11 Device and Documentation Support 11.1 Device Support 11.1.1 Development Support 11.1.1.1 TINA-TI™ (Free Software Download) 11.1.1.2 TI Precision Designs 11.2 Documentation Support 11.2.1 Related Documentation 11.3 Receiving Notification of Documentation Updates 11.4 Support Resources 11.5 Trademarks 11.6 Electrostatic Discharge Caution 11.7 Glossary 12 Mechanical, Packaging, and Orderable Information