Datasheet TPLD1201 (Texas Instruments) - 3

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TPLD1201 www.ti.com
SCPS287B – NOVEMBER 2023 – REVISED DECEMBER 2024
4 Pin Configuration and Functions
GPIO9 NC 2 1 VCC 3 12 GPIO7 GPI 4 11 GPIO6 GPIO1 5 10 GPIO5 GPIO2 6 9 GND 7 8 Not to scale NC GPIO4
Figure 4-1. RWB Package, 12-Pin X2QFN (Top View)
GPI 1 10 VCC GPIO1 2 9 GPIO9 GPIO2 3 8 GPIO7 GPIO4 4 7 GPIO6 GND 5 6 GPIO5 Not to scale
Figure 4-2. DGS Package, 10-Pin VSSOP (Top View) Table 4-1. Pin Functions PIN DESCRIPTION NAME RWB DGS TYPE
(1)
Primary function Secondary function (if any)
GPI 4 1 I General-purpose input(3) IO1 5 2 I/O General-purpose I/O ACMP0 IN+ IO2 6 3 I/O General-purpose I/O External VREF IN/ACMP0 or ACMP1 IN- IO4 8 4 I/O General-purpose I/O with output enable (OE)(4) ACMP1 IN+ GND 9 5 P Ground IO5 10 6 I/O General-purpose I/O IO6 11 7 I/O General-purpose I/O IO7 12 8 I/O General-purpose I/O with output enable (OE)(4) Internal VREF OUT IO9 2 9 I/O General-purpose I/O External OSC IN VCC 3 10 P Supply voltage NC 1 — — Not internally connected(2) NC 7 — — Not internally connected(2) (1) P = power, I/O = input/output, I = Input (2) Pins not internally connected must be grounded or left floating (3) The general-purpose input (GPI) pin will sustain a high-voltage (VPP) during programming. Take special precaution with peripherals connected to this pin if performing in-system programming. (4) The output enable (OE) connection is available through the connection mux and can be configured in InterConnect Studio. Copyright © 2024 Texas Instruments Incorporated Submit Document Feedback 3 Product Folder Links: TPLD1201 Document Outline 1 Features 2 Applications 3 Description Table of Contents 4 Pin Configuration and Functions 5 Specifications 5.1 Absolute Maximum Ratings 5.2 ESD Ratings 5.3 Recommended Operating Conditions 5.4 Thermal Information 5.5 Electrical Characteristics 5.6 Supply Current Characteristics 5.7 Switching Characteristics 5.8 Typical Characteristics 6 Parameter Measurement Information 7 Detailed Description 7.1 Overview 7.2 Functional Block Diagram 7.3 Feature Description 7.3.1 I/O Pins 7.3.2 Connection Mux 7.3.3 Configurable Use Logic Blocks 7.3.3.1 2-Bit LUT Macro-Cell 7.3.3.2 3-Bit LUT Macro-Cell 7.3.3.3 2-Bit LUT or D Flip-Flop or Latch Macro-Cell 7.3.3.4 3-Bit LUT or D Flip-Flop or Latch with Set or Reset Macro-Cell 7.3.3.5 3-Bit LUT or Pipe Delay Macro-cell 7.3.3.6 4-Bit LUT or 8-Bit Counter or Delay Macro-Cell 7.3.4 8-Bit Counters and Delay Generators (CNT/DLY) 7.3.4.1 Delay Mode 7.3.4.2 Edge Detector Mode 7.3.4.3 Reset Counter Mode 7.3.5 Programmable Deglitch Filter or Edge Detector Macro-cell 7.3.6 Selectable Frequency Oscillator 7.3.7 Analog Comparators (ACMP) 7.3.8 Voltage Reference (VREF) 7.4 Device Functional Modes 7.4.1 Power-On Reset 8 Application and Implementation 8.1 Application Information 8.2 Typical Application 8.2.1 Design Requirements 8.2.1.1 Power Considerations 8.2.1.2 Input Considerations 8.2.1.3 Output Considerations 8.2.2 Detailed Design Procedure 8.2.3 Application Curves 8.3 Power Supply Recommendations 8.4 Layout 8.4.1 Layout Guidelines 8.4.2 Layout Example 9 Device and Documentation Support 9.1 Receiving Notification of Documentation Updates 9.2 Support Resources 9.3 Trademarks 9.4 Electrostatic Discharge Caution 9.5 Glossary 10 Revision History 11 Mechanical, Packaging, and Orderable Information 11.1 Packaging Option Addendum 11.2 Tape and Reel Information 11.3 Mechanical Data