Datasheet TPLD1201 (Texas Instruments) - 5

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TPLD1201 www.ti.com
SCPS287B – NOVEMBER 2023 – REVISED DECEMBER 2024 over operating free-air temperature range (unless otherwise noted)
VCC MIN MAX UNIT
TA Ambient temperature –40 125 °C
5.4 Thermal Information TPLD1201 THERMAL METRIC
(1)
RWB (X2QFN) DGS (VSSOP) UNIT 12-PIN 10-PIN
RθJA Junction-to-ambient thermal resistance 157.6 152.7 °C/W RθJC(top) Junction-to-case (top) thermal resistance 50.3 60.8 °C/W RθJB Junction-to-board thermal resistance 95.5 88.9 °C/W ΨJT Junction-to-top characterization parameter 0.8 4.8 °C/W ΨJB Junction-to-board characterization parameter 95.5 87.2 °C/W RθJC(bot) Junction-to-case (bottom) thermal resistance °C/W (1) For more information about traditional and new thermal metrics, see the Semiconductor and IC Package Thermal Metrics application report.
5.5 Electrical Characteristics
over operating free-air temperature range (unless otherwise noted)
TEST PARAMETER V CONDITIONS CC MIN TYP MAX UNIT Supply and Power-on Reset
V V I = VCC or PORR Power-on reset voltage, VCC rising 1.71V to 5.5V 1.25 1.30 1.40 V GND, IO = 0 V V I = VCC or PORF Power-on reset voltage, VCC falling 1.71V to 5.5V 1.20 1.26 1.35 V GND, IO = 0 from V t CC rising SU Startup time 1.71V to 5.5V 245 µs past VPORR VPP Programming voltage 7.5 8 V
Digital IO
1.8V ± 0.09V 0.94 1.27 Positive-going input Logic Input with Schmitt VT+ 3.3V ± 0.3V 1.55 2.30 V threshold voltage Trigger 5V ± 0.5V 2.21 3.19 1.8V ± 0.09V 0.58 0.94 Negative-going input Logic Input with Schmitt VT- 3.3V ± 0.3V 1.1 1.79 V threshold voltage Trigger 5V ± 0.5V 1.63 2.7 1.8V ± 0.09V 0.20 0.51 Schmitt trigger hysteresis Logic Input with Schmitt VHYS 3.3V ± 0.3V 0.33 0.61 V (VT+ − VT−) Trigger 5V ± 0.5V 0.42 0.75 Hysteresis voltage VHYS GPI Hysteresis Voltage 1.71V to 5.5V 0.2 V applicable to the IN0 Copyright © 2024 Texas Instruments Incorporated Submit Document Feedback 5 Product Folder Links: TPLD1201 Document Outline 1 Features 2 Applications 3 Description Table of Contents 4 Pin Configuration and Functions 5 Specifications 5.1 Absolute Maximum Ratings 5.2 ESD Ratings 5.3 Recommended Operating Conditions 5.4 Thermal Information 5.5 Electrical Characteristics 5.6 Supply Current Characteristics 5.7 Switching Characteristics 5.8 Typical Characteristics 6 Parameter Measurement Information 7 Detailed Description 7.1 Overview 7.2 Functional Block Diagram 7.3 Feature Description 7.3.1 I/O Pins 7.3.2 Connection Mux 7.3.3 Configurable Use Logic Blocks 7.3.3.1 2-Bit LUT Macro-Cell 7.3.3.2 3-Bit LUT Macro-Cell 7.3.3.3 2-Bit LUT or D Flip-Flop or Latch Macro-Cell 7.3.3.4 3-Bit LUT or D Flip-Flop or Latch with Set or Reset Macro-Cell 7.3.3.5 3-Bit LUT or Pipe Delay Macro-cell 7.3.3.6 4-Bit LUT or 8-Bit Counter or Delay Macro-Cell 7.3.4 8-Bit Counters and Delay Generators (CNT/DLY) 7.3.4.1 Delay Mode 7.3.4.2 Edge Detector Mode 7.3.4.3 Reset Counter Mode 7.3.5 Programmable Deglitch Filter or Edge Detector Macro-cell 7.3.6 Selectable Frequency Oscillator 7.3.7 Analog Comparators (ACMP) 7.3.8 Voltage Reference (VREF) 7.4 Device Functional Modes 7.4.1 Power-On Reset 8 Application and Implementation 8.1 Application Information 8.2 Typical Application 8.2.1 Design Requirements 8.2.1.1 Power Considerations 8.2.1.2 Input Considerations 8.2.1.3 Output Considerations 8.2.2 Detailed Design Procedure 8.2.3 Application Curves 8.3 Power Supply Recommendations 8.4 Layout 8.4.1 Layout Guidelines 8.4.2 Layout Example 9 Device and Documentation Support 9.1 Receiving Notification of Documentation Updates 9.2 Support Resources 9.3 Trademarks 9.4 Electrostatic Discharge Caution 9.5 Glossary 10 Revision History 11 Mechanical, Packaging, and Orderable Information 11.1 Packaging Option Addendum 11.2 Tape and Reel Information 11.3 Mechanical Data