Datasheet BUF802 (Texas Instruments) - 3

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BUF802 www.ti.com
SBOS998C – JUNE 2021 – REVISED MARCH 2022
5 Pin Configuration and Functions
NC CLH CLL NC 16 15 14 13 13 14 15 16 VS+ 1 12 VSO+ 12 1 Clamp Diode Output OUT IN 2 11 Stage 11 2 JFET THERMAL PAD IN_Bias 3 10 VSO- 10 3 I2 I1 IN_Aux 4 9 NC 9 4 5 6 7 8 8 7 6 5 8 VS- Aux_Bias R_Bias VS- *Pin 5 and Pin 8 Internally Shorted
Figure 5-1. RGT Package, 16-Pin VQFN (Top View and Bottom View) Table 5-1. Pin Functions PIN TYPE
(4)
Operating Mode
(1) (2)
DESCRIPTION NAME NO.
Aux_Bias 6 P CL Connect to VS- to enable control of OUT through the In_Aux. CLH 15 I BF, CL Input pin for setting positive clamp voltage CLL 14 I BF, CL Input pin for setting negative clamp voltage IN 2 I BF, CL Signal input In_Aux 4 I CL Auxiliary input for controlling OUT through an external amplifier. In_Bias 3 I CL JFET biasing pin NC 16, 13, 9 — — Do not connect. OUT 11 O BF, CL Signal output R_Bias 7 I BF, CL Output stage bias current setting pin VS+ 1 P BF, CL Positive power supply connection for Input Stage. Negative power supply connection for Input Stage. Pin 5 and Pin 8 are VS- 5, 8 P BF, CL internally shorted. VSO+ (3) 12 P BF, CL Positive power supply connection for Output Stage. VSO- (3) 10 P BF, CL Negative power supply connection for Output Stage. The thermal pad is electrically isolated from the die and pins. Connect the Thermal Pad — — thermal pad to any potential. (1) See Section 8.4 for more information on Buffer Mode (BF) and Composite Loop Mode (CL) functional modes. (2) Pins specified as CL should only be used when operating in Composite Loop Mode and left floating when operating in Buffer Mode. (3) VSO and VS should be tied to the same potential since they are internally connected to each other through back-to-back diodes. (4) I = input, O= output, P= power, NC = no connect. Copyright © 2022 Texas Instruments Incorporated Submit Document Feedback 3 Product Folder Links: BUF802 Document Outline 1 Features 2 Applications 3 Description Table of Contents 4 Revision History 5 Pin Configuration and Functions 6 Specifications 6.1 Absolute Maximum Ratings 6.2 ESD Ratings 6.3 Recommended Operating Conditions 6.4 Thermal Information 6.5 Electrical Characteristics: Wide Bandwidth Mode 6.6 Electrical Characteristics: Low Quiescent Current Mode 6.7 Typical Characteristics 7 Parameter Measurement Information 8 Detailed Description 8.1 Overview 8.2 Functional Block Diagram 8.3 Feature Description 8.3.1 Input and Output Over-Voltage Clamp 8.3.2 Adjustable Quiescent Current 8.3.3 ESD Structure 8.4 Device Functional Modes 8.4.1 Buffer Mode (BF Mode) 8.4.2 Composite Loop Mode (CL Mode) 9 Application and Implementation 9.1 Application Information 9.2 Typical Application 9.2.1 Oscilloscope Front-End Amplifier Design 9.2.1.1 Design Requirements 9.2.1.2 Detailed Design Procedure 9.2.1.3 Application Curves 9.2.2 Transforming a Wide-Bandwidth, 50 Ω Input Signal Chain to High-Input Impedance 9.2.2.1 Detailed Design Results 9.2.2.2 Application Curves 10 Power Supply Recommendations 11 Layout 11.1 Layout Guidelines 11.2 Layout Example 12 Device and Documentation Support 12.1 Documentation Support 12.1.1 Related Documentation 12.2 Receiving Notification of Documentation Updates 12.3 Support Resources 12.4 Trademarks 12.5 Electrostatic Discharge Caution 12.6 Glossary 13 Mechanical, Packaging, and Orderable Information