Datasheet MC74AC125, MC74ACT125 (ON Semiconductor)
| 制造商 | ON Semiconductor |
| 描述 | Quad 3-State Buffer with Low Enable |
| 页数 / 页 | 9 / 1 — DATA SHEET. www.onsemi.com. MARKING. DIAGRAMS. SOIC−14. D SUFFIX. CASE … |
| 文件格式/大小 | PDF / 245 Kb |
| 文件语言 | 英语 |
DATA SHEET. www.onsemi.com. MARKING. DIAGRAMS. SOIC−14. D SUFFIX. CASE 751A. Features. TSSOP−14. DT SUFFIX. CASE 948G. ORDERING INFORMATION
该数据表的模型线
文件文字版本
link to page 5
DATA SHEET www.onsemi.com
Quad 3-State Buffer with
MARKING DIAGRAMS
Low Enable 14 High-Performance Silicon-Gate
SOIC−14
XXXXXXG
D SUFFIX
AWLYWW CMOS
CASE 751A
14 1 1 MC74AC125, MC74ACT125 14
Features
XXX •
TSSOP−14
XXX Outputs Source/Sink
DT SUFFIX
ALYWG • ′ACT125 Has TTL Compatible Inputs 1
CASE 948G
G • These are Pb−Free Devices 14 1 XXXXXX = Specific Device Code A = Assembly Location WL or L = Wafer Lot VCC A2 B2 O2 A3 B3 O3 Y = Year WW or W = Work Week 14 13 12 11 10 9 8 G or G = Pb−Free Package (Note: Microdot may be in either location)
ORDERING INFORMATION
See detailed ordering and shipping information in the package 1 2 3 4 5 6 7 dimensions section on page 5 of this data sheet. A0 B0 O0 A1 B1 O1 GND
Figure 1. Pinout: 14−Lead Packages Conductors
(Top View)
PIN ASSIGNMENT PIN FUNCTION
An, Bn Inputs On Outputs
FUNCTION TABLE Inputs Output An Bn On
L L L L H H H X Z NOTE: H = High Voltage Level; L = Low Voltage Level; Z = High Impedance; X = Immaterial © Semiconductor Components Industries, LLC, 2015
1
Publication Order Number:
February, 2024 − Rev. 9 MC74AC125/D
DATA SHEET www.onsemi.com
Quad 3-State Buffer with
MARKING DIAGRAMS
Low Enable 14 High-Performance Silicon-Gate
SOIC−14
XXXXXXG
D SUFFIX
AWLYWW CMOS
CASE 751A
14 1 1 MC74AC125, MC74ACT125 14
Features
XXX •
TSSOP−14
XXX Outputs Source/Sink
DT SUFFIX
ALYWG • ′ACT125 Has TTL Compatible Inputs 1
CASE 948G
G • These are Pb−Free Devices 14 1 XXXXXX = Specific Device Code A = Assembly Location WL or L = Wafer Lot VCC A2 B2 O2 A3 B3 O3 Y = Year WW or W = Work Week 14 13 12 11 10 9 8 G or G = Pb−Free Package (Note: Microdot may be in either location)
ORDERING INFORMATION
See detailed ordering and shipping information in the package 1 2 3 4 5 6 7 dimensions section on page 5 of this data sheet. A0 B0 O0 A1 B1 O1 GND
Figure 1. Pinout: 14−Lead Packages Conductors
(Top View)
PIN ASSIGNMENT PIN FUNCTION
An, Bn Inputs On Outputs
FUNCTION TABLE Inputs Output An Bn On
L L L L H H H X Z NOTE: H = High Voltage Level; L = Low Voltage Level; Z = High Impedance; X = Immaterial © Semiconductor Components Industries, LLC, 2015
1
Publication Order Number:
February, 2024 − Rev. 9 MC74AC125/D